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AD7821BQ 数据表(PDF) 3 Page - Analog Devices |
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AD7821BQ 数据表(HTML) 3 Page - Analog Devices |
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3 / 12 page  AD7821 REV. A –3– TIMING CHARACTERISTICS1 (V DD = +5 V ± 5%, VSS = 0 V or –5 V ± 5%; Unipolar or Bipolar Input Range) Limit at Limit at Limit at +25 CTMIN, TMAX TMIN, TMAX Parameter (All Versions) (K, B Versions) (T Version) Units Conditions/Comments tCSS 0 0 0 ns min CS to RD/WR Setup Time tCSH 0 0 0 ns min CS to RD/WR Hold Time tRDY 2 70 85 100 ns max CS to RDY Delay. Pull-Up Resistor 5 k1. tCRD 700 875 975 ns max Conversion Time (RD Mode) tACC0 3 Data Access Time (RD Mode) tCRD + 25 tCRD + 30 tCRD + 35 ns max CL = 20 pF tCRD + 50 tCRD + 65 tCRD + 75 ns max CL = 100 pF tINTH 2 50 – – ns typ RD to INT Delay (RD Mode) 80 85 90 ns max tDH 4 15 15 15 ns min Data Hold Time 60 70 80 ns max tP 350 425 500 ns min Delay Time Between Conversions tWR 250 325 400 ns min Write Pulse Width 10 10 10 µs max tRD 250 350 450 ns min Delay Time between WR and RD Pulses tREAD1 160 205 240 ns min RD Pulse Width (WR-RD Mode, see Figure 12b) Determined by tACC1 tACC1 3 Data Access Time (WR-RD Mode, see Figure 12b) 160 205 240 ns max CL = 20 pF 185 235 275 ns max CL = 100 pF tRI 150 185 220 ns max RD to INT Delay tINTL 2 380 – – ns typ WR to INT Delay 500 610 700 ns max tREAD2 65 75 85 ns min RD Pulse Width (WR-RD Mode, see Figure 12a) Determined by tACC2 Data Access Time (WR-RD Mode, see Figure 12a) tACC2 3 65 75 85 ns max CL = 20 pF 90 110 130 ns max CL = 100 pF tIHWR 2 80 100 120 ns max WR to INT Delay (Stand-Alone Operation) tID 3 Data Access Time after INT (Stand-Alone Operation) 30 35 40 ns max CL = 20 pF 45 60 70 ns max CL = 100 pF NOTES 1Sample tested at +25 °C to ensure compliance. All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 2C L = 50 pF. 3Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 4Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2. Specifications subject to change without notice. Test Circuits a. High Z to VOH b. High Z to VOL Figure 1. Load Circuits for Data Access Time Test a. VOH to High Z b. VOL to High Z Figure 2. Load Circuits for Data Hold Time Test ORDERING GUIDE Total Temperature Unadjusted Package Model1 Range Error (LSB) Option2 AD7821KN –40 °C to +85°C ±1 max N-20 AD7821KP –40 °C to +85°C ±1 max P-20A AD7821KR –40 °C to +85°C ±1 max R-20 AD7821BQ –40 °C to +85°C ±1 max Q-20 AD7821TQ –55 °C to +125°C ±1 max Q-20 AD7821TE –55 °C to +125°C ±1 max E-20A NOTES 1To order MIL-STD-883, Class B processed parts, add /883B to part number. Contact local sales office for military data sheet. 2E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC. |
类似零件编号 - AD7821BQ |
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类似说明 - AD7821BQ |
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