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AD7394 数据表(PDF) 4 Page - Analog Devices |
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AD7394 数据表(HTML) 4 Page - Analog Devices |
4 / 12 page AD7394/AD7395 –4– REV. 0 Table I. Control Logic Truth Table CS CLK RS MSB SHDN LDA/B Serial Shift Register Function DAC Register Function H X H X H H No Effect Latched L L H X H H No Effect Latched L H H X H H No Effect Latched L ↑+ H X H H Shift-Register-Data Advanced One Bit Latched L ↑+ H X H L Shift-Register-Data Advanced One Bit Transparent L H H X H L No Effect Transparent ↑+ L H X H H No Effect Latched HX H X H ↓– No Effect Updated with Current Shift Register Contents H X H X H L No Effect Transparent X X L H H X No Effect Loaded with 800H XX ↑+ H H H No Effect Latched with 800H X X L L H X No Effect Loaded with All Zeros XX ↑+ L H H No Effect Latched All Zeros X X X X L X No Effect No Affect NOTES 1. ↑+ positive logic transition; ↓– negative logic transition; X Don’t Care 2. Do not clock in serial data while level sensitive inputs LDA or LDB are logic LOW. tLD1 tCSH 1 LSB ERROR BAND tCLRW tS tS tLDW tCH tCL tCSS tLD2 tDS tDH D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 SDI CLK CS LDA,B SDI CLK FS VOUT ZS LDA,B RS Figure 2. Timing Diagram tSDR IDD SHDN Figure 3. Timing Diagram |
类似零件编号 - AD7394 |
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类似说明 - AD7394 |
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