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AD73322LAST 数据表(PDF) 11 Page - Analog Devices |
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AD73322LAST 数据表(HTML) 11 Page - Analog Devices |
11 / 40 page REV. 0 AD73322L –11– FUNCTIONAL DESCRIPTION Encoder Channels Both encoder channels consist of a pair of inverting op amps with feedback connections that can be bypassed if required, a switched capacitor PGA and a sigma-delta analog-to-digital converter (ADC). An on-board digital filter, which forms part of the sigma-delta ADC, also performs critical system-level filtering. Due to the high level of oversampling, the input antialias require- ments are reduced such that a simple single pole RC stage is sufficient to give adequate attenuation in the band of interest. Programmable Gain Amplifier Each encoder section’s analog front end comprises a switched capacitor PGA, which also forms part of the sigma-delta modula- tor. The SC sampling frequency is DMCLK/8. The PGA, whose programmable gain settings are shown in Table III, may be used to increase the signal level applied to the ADC from low output sources such as microphones, and can be used to avoid placing external amplifiers in the circuit. The input signal level to the sigma-delta modulator should not exceed the maximum input voltage permitted. The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0–2) in control register D. Table III. PGA Settings for the Encoder Channel IGS2 IGS1 IGS0 Gain (dB) 00 0 0 00 1 6 01 0 12 01 1 18 10 0 20 10 1 26 11 0 32 11 1 38 ADC Both ADCs consist of an analog sigma-delta modulator and a digital antialiasing decimation filter. The sigma-delta modu- lator noise-shapes the signal and produces 1-bit samples at a DMCLK/8 rate. This bitstream, representing the analog input signal, is input to the antialiasing decimation filter. The decimation filter reduces the sample rate and increases the resolution. Analog Sigma-Delta Modulator The AD73322L’s input channels employ a sigma-delta conversion technique, which provides a high resolution 16-bit output with system filtering being implemented on-chip. Sigma-delta converters employ a technique known as over- sampling, where the sampling rate is many times the highest frequency of interest. In the case of the AD73322L, the initial sampling rate of the sigma-delta modulator is DMCLK/8. The main effect of oversampling is that the quantization noise is spread over a very wide bandwidth, up to FS/2 = DMCLK/16 (Figure 7a). This means that the noise in the band of interest is much reduced. Another complementary feature of sigma-delta converters is the use of a technique called noise-shaping. This technique has the effect of pushing the noise from the band of interest to an out-of-band position (Figure 7b). The combina- tion of these techniques, followed by the application of a digital filter, sufficiently reduces the noise in band to ensure good dynamic performance from the part (Figure 7c). BAND OF INTEREST FS/2 DMCLK/16 FS/2 DMCLK/16 FS/2 DMCLK/16 DIGITAL FILTER NOISE SHAPING BAND OF INTEREST BAND OF INTEREST a. b. c. Figure 6. Sigma-Delta Noise Reduction Figure 7 shows the various stages of filtering that are employed in a typical AD73322L application. In Figure 7a we see the trans- fer function of the external analog antialias filter. Even though it is a single RC pole, its cutoff frequency is sufficiently far away from the initial sampling frequency (DMCLK/8) that it takes care of any signals that could be aliased by the sampling fre- quency. This also shows the major difference between the initial oversampling rate and the bandwidth of interest. In Figure 7b, the signal and noise-shaping responses of the sigma-delta modu- lator are shown. The signal response provides further rejection of any high frequency signals while the noise-shaping will push the inherent quantization noise to an out-of-band position. The detail of Figure 7c shows the response of the digital decimation filter (Sinc-cubed response) with nulls every multiple of DMCLK/ 256, which corresponds to the decimation filter update rate for a 64 kHz sampling. The nulls of the Sinc3 response corre- spond with multiples of the chosen sampling frequency. The final detail in Figure 7d shows the application of a final anti- alias filter in the DSP engine. This has the advantage of being implemented according to the user’s requirements and available MIPS. The filtering in Figures 7a through 7c is implemented in the AD73322L. |
类似零件编号 - AD73322LAST |
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类似说明 - AD73322LAST |
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