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AD73322 数据表(PDF) 9 Page - Analog Devices |
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AD73322 数据表(HTML) 9 Page - Analog Devices |
9 / 43 page AD73322 –9– REV. B TIMING CHARACTERISTICS Limit at Parameter TA = –40 C to +85 C Units Description Clock Signals See Figure 1 t1 61 ns min MCLK Period t2 24.4 ns min MCLK Width High t3 24.4 ns min MCLK Width Low Serial Port See Figures 3 and 4 t4 t1 ns min SCLK Period t5 0.4 × t 1 ns min SCLK Width High t6 0.4 × t 1 ns min SCLK Width Low t7 20 ns typ SDI/SDIFS Setup Before SCLK Low t8 0 ns typ SDI/SDIFS Hold After SCLK Low t9 10 ns typ SDOFS Delay from SCLK High t10 10 ns typ SDOFS Hold After SCLK High t11 10 ns typ SDO Hold After SCLK High t12 10 ns typ SDO Delay from SCLK High t13 30 ns typ SCLK Delay from MCLK Specifications subject to change without notice. (AVDD = +5 V 10%; DVDD = +5 V 10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless otherwise noted) t3 t2 t1 Figure 1. MCLK Timing t11 t7 t9 t10 t7 t8 t8 SE (I) SCLK (O) SDIFS (I) SDI (I) SDOFS (O) SDO (O) THREE- STATE THREE- STATE THREE- STATE D15 D2D1D0 D14 D15 D0 D1 D14 D15 D15 t12 Figure 4. Serial Port (SPORT) t3 t1 t2 t13 * SCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE). t4 t5 t6 MCLK SCLK* Figure 3. SCLK Timing TO OUTPUT PIN +2.1V 100 A 100 A IOL IOH CL 15pF Figure 2. Load Circuit for Timing Specifications |
类似零件编号 - AD73322 |
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类似说明 - AD73322 |
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