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AD712KN 数据表(PDF) 7 Page - Analog Devices |
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AD712KN 数据表(HTML) 7 Page - Analog Devices |
7 / 15 page AD712 REV. B –7– OPTIMIZING SETTLING TIME Most bipolar high-speed D/A converters have current outputs; therefore, for most applications, an external op amp is required for current-to-voltage conversion. The settling time of the con- verter/op amp combination depends on the settling time of the DAC and output amplifier. A good approximation is: t S Total = (t S DAC ) 2 + (t S AMP ) 2 The settling time of an op amp DAC buffer will vary with the noise gain of the circuit, the DAC output capacitance, and with the amount of external compensation capacitance across the DAC output scaling resistor. Settling time for a bipolar DAC is typically 100 ns to 500 ns. Previously, conventional op amps have required much longer settling times than have typical state-of-the-art DACs; therefore, the amplifier settling time has been the major limitation to a high-speed voltage-output D-to-A function. The introduction of the AD711/AD712 family of op amps with their 1 µs (to ±0.01% of final value) settling time now permits the full high-speed capabilities of most modern DACs to be realized. In addition to a significant improvement in settling time, the low offset voltage, low offset voltage drift, and high open-loop gain of the AD711/AD712 family assures 12-bit accuracy over the full operating temperature range. The excellent high-speed performance of the AD712 is shown in the oscilloscope photos of Figure 25. Measurements were taken using a low input capacitance amplifier connected directly to the summing junction of the AD712 – both photos show the worst case situation: a full-scale input transition. The DAC’s 4 k Ω [10 k Ω||8 kΩ = 4.4 kΩ] output impedance together with a 10 k Ω feedback resistor produce an op amp noise gain of 3.25. The current output from the DAC produces a 10 V step at the op amp output (0 to –10 V Figure 25a, –10 V to 0 V Figure 25b.) Therefore, with an ideal op amp, settling to ±1/2 LSB (±0.01%) requires that 375 µV or less appears at the summing junction. This means that the error between the input and output (that voltage which appears at the AD712 summing junction) must be less than 375 µV. As shown in Figure 25, the total settling time for the AD712/AD565 combination is 1.2 microseconds. +15V 0.1 F 0.1 F 1/2 AD712 10pF OUTPUT –10V TO +10V AD565A DAC –15V IOUT = 4 IREF CODE IREF BIPOLAR OFFSET ADJUST IO 0.1 F R1 100 R2 100 GAIN ADJUST REF IN REF GND 20k –VEE 0.1 F POWER GND MSB LSB 8k 5k 5k 10V 19.95k 0.5mA DAC OUT 10V SPAN 20V SPAN VCC REF OUT BIPOLAR OFF 9.95k + – Figure 24. ±10 V Voltage Output Bipolar DAC Figure 25. Settling Characteristics for AD712 with AD565A 100 10 0% 500ns 90 0V –10V OUTPUT 5V 1mV SUMMING JUNCTION a. (Full-Scale Negative Transition) 100 10 0% 500ns 90 0V –10V SUMMING JUNCTION OUTPUT 5V 1mV b. (Full-Scale Positive Transition) |
类似零件编号 - AD712KN |
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类似说明 - AD712KN |
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