AD7112CN datasheet(3/12 Pages) AD

部件名	AD7112CN

功能描述	LC2MOS LOGDAC Dual Logarithmic D/A Converter

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制造商	AD [Analog Devices]

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AD7112

REV. 0

–3–

TIMING SPECIFICATIONS1

Parameter

TA = +25 CTA = –40 C to +85 C

Units

Conditions/Comments

CS

to WR Setup Time

tCS

0

ns min

See Figure 3.

CS

to WR Hold Time

tCH

0

ns min

DAC Select to WR Setup Time

tAS

4

ns min

DAC Select to WR Hold Time

tAH

0

ns min

Data Valid to WR Setup Time

tDS

55

ns min

Data Valid to WR Hold Time

tDH

10

ns min

WR

Pulse Width

tWR

53

ns min

NOTES

1Timing specifications guaranteed by design not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage

level of 1.6 V.

Specifications subject to change without notice.

AC PERFORMANCE CHARACTERISTICS1

TA =

–40 C to

Parameter

+25 C

+85 C

Units

Conditions/Comments

DC Supply Rejection

∆ Gain/∆ V

DD

0.001

0.005

dB/% max

∆ V

DD = ± 5%. Input Code = 00000000

Digital-to-Analog Glitch Impulse

10

nV s typ

Measured with AD843 as output amplifier for input

code transition 10000000 to 00000000.

Output Capacitance, COUT A, COUT B

50

pF max

AC Feedthrough

VIN A to OUT A

–94

–90

dB max

VIN A, VIN B = 6 V rms at 1 kHz. DAC

Registers loaded with all 1s.

VIN B to OUT B

–94

–90

dB max

Channel-to-Channel Isolation

VIN A to OUT B

–87

dB typ

VIN A = 6 V rms at 10 kHz sine wave,

VIN B = 0 V. DAC Registers loaded with all 0s.

VIN B to OUT A

–87

dB typ

VIN B = 6 V rms at 10 kHz sine wave,

VIN A = 0 V. DAC Registers loaded with all 0s.

Digital Feedthrough

1

nV s typ

Measured with input code transitions of all 0s to all 1s.

Output Noise Voltage Density

(30 Hz to 50 kHz)

15

nV/

√Hz typ Measured between R

FB A and OUT A or between

RFB B and OUT B.

Total Harmonic Distortion

–91

dB typ

VIN A = VIN B = 6 V rms at 1 kHz. DAC

Registers loaded with all 0s.

NOTES

1Guaranteed by design, not production tested.

Specifications subject to change without notice.

(VDD = +5 V

5%; 0UT A = OUT B = AGND = DGND = O V; VIN A = VIN B = 10 V)

(VDD = +5 V

5%; 0UT A = OUT B = AGND = DGND = 0 V; VIN A =

VIN B = 10 V. Output amplifier AD712 except where noted.)

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制造商	部件名	数据表	功能描述
Analog Devices	AD7112	572Kb / 12P	LC MOS LOGDAC DUAL LOGARITHMIC D/A CONVERTER REV. 0

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