AD679TJ datasheet(4/12 Pages) AD

部件名	AD679TJ

功能描述	14-Bit 128 kSPS Complete Sampling ADC

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制造商	AD [Analog Devices]

网页	http://www.analog.com

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AD679

REV. C

–4–

TIMING SPECIFICATIONS

(All device types TMIN to TMAX, VCC = +12 V

5%, VEE = –12 V

5%,

VDD = +5 V

10%)

Parameter

Symbol

Min

Max

Units

SC

Delay

tSC

50

ns

Conversion Time

tC

6.3

µs

Conversion Rate1

tCR

7.8

µs

Convert Pulse Width

tCP

0.097

3.0

µs

Aperture Delay

tAD

520

ns

Status Delay

tSD

0

400

ns

Access Time2, 3

tBA

10

100

ns

10

574

ns

Float Delay5

tFD

10

80

ns

Output Delay

tOD

0ns

Format Setup

tFS

100

ns

OE

Delay

tOE

20

ns

Read Pulse Width

tRP

195

ns

Conversion Delay

tCD

400

ns

EOCEN

Delay

tEO

50

ns

NOTES

1Includes Acquisition Time.

2Measured from the falling edge of OE/EOCEN (0.8 V) to the time at which the

data lines/EOC cross 2.0 V or 0.8 V. See Figure 4.

3C

OUT = 100 pF.

4C

OUT = 50 pF.

5Measured from the rising edge of OE/EOCEN (2.0 V) to the time at which the

output voltage changes by 0.5. See Figure 4; COUT = 10 pF.

Specifications subject to change without notice.

ORDERING GUIDE

1

Tested

Temperature

and

Package

Model

2

Package

Range

Specified

Option

3

AD679JN

28-Pin Plastic DIP

0

°C to +70°C

AC

N-28

AD679KN 28-Pin Plastic DIP

0

°C to +70°C

AC + DC

N-28

AD679JD

28-Pin Ceramic DIP

0

°C to +70°C

AC

D-28

AD679KD 28-Pin Ceramic DIP

0

°C to +70°C

AC + DC

D-28

AD679AD 28-Pin Ceramic DIP

–40

°C to +85°C

AC

D-28

AD679BD 28-Pin Ceramic DIP

–40

°C to +85°C

AC + DC

D-28

AD679SD 28-Pin Ceramic DIP

–55

°C to +125°C AC

D-28

AD679TD 28-Pin Ceramic DIP

–55

°C to +125°C AC + DC D-28

AD679AJ

44-Lead Ceramic JLCC

–40

°C to +85°C

AC

J-44

AD679BJ

44-Lead Ceramic JLCC

–40

°C to +85°C

AC + DC

J-44

AD679SJ

44-Lead Ceramic JLCC

–55

°C to +125°C AC

J-44

AD679TJ

44-Lead Ceramic JLCC

–55

°C to +125°C AC + DC J-44

NOTES

1For parallel read (14-bits) interface to 16-bit buses, see AD779.

2For details grade and package offerings screened in accordance with MIL-STD-

883, refer to the Analog Devices Miliary Products Databook or current AD679/

883B data sheet.

3N = Plastic DIP; D = Ceramic DIP; J = J-Leaded Ceramic Chip Carrier.

Figure 1. Conversion Timing

Figure 2. Output Timing

Figure 3. EOC Timing

Figure 4. Load Circuit for Bus Timing Specifications

类似零件编号 - AD679TJ

制造商	部件名	数据表	功能描述
Analog Devices	AD679TD	161Kb / 16P	14-Bit 128 kSPS Complete Sampling ADC REV. D

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Analog Devices	AD679	161Kb / 16P	14-Bit 128 kSPS Complete Sampling ADC REV. D
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