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AD669AN 数据表(PDF) 3 Page - Analog Devices |
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AD669AN 数据表(HTML) 3 Page - Analog Devices |
3 / 12 page AD669 REV. A –3– TIMING CHARACTERISTICS VCC = +15 V, VEE = –15 V, VLL = +5 V, VHI = 2.4 V, VLO = 0.4 V Limit Limit Limit –40 C to –55 C to Parameter +25 C +85 C +125 C Units (Figure la) tCS 40 50 55 ns min tLI 40 50 55 ns min tDS 30 35 40 ns min tDH 10 10 15 ns min tLH 90 110 120 ns min tLW 40 45 45 ns min (Figure lb) tLOW 130 150 165 ns min tHIGH 40 45 45 ns min tDS 120 140 150 ns min tDH 10 10 15 ns min Specifications subject to change without notice. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed. Those shown in boldface are tested on all production units. AC PERFORMANCE CHARACTERISTICS Parameter Limit Units Test Conditions/Comments Output Settling Time 13 µs max 20 V Step, TA = +25 °C (Time to ±0.0008% FS 8 µs typ 20 V Step, TA = +25°C with 2 k Ω, 1000 pF Load) 10 µs typ 20 V Step, TMIN ≤ T A ≤ T MAX 6 µs typ 10 V Step, TA = +25 °C 8 µs typ 10 V Step, TMIN ≤ TA ≤ TMAX 2.5 µs typ 1 LSB Step, TMIN ≤ T A ≤ T MAX Total Harmonic Distortion + Noise A, B, S Grade 0.009 % max 0 dB, 1001 Hz; Sample Rate = 100 kHz; TA = +25 °C A, B, S Grade 0.07 % max –20 dB, 1001 Hz; Sample Rate = 100 kHz; TA = +25 °C A, B, S Grade 7.0 % max –60 dB, 1001 Hz; Sample Rate = 100 kHz; TA = +25°C Signal-to-Noise Ratio 83 dB min TA = +25°C Digital-to-Analog Glitch Impulse 15 nV-s typ DAC Alternately Loaded with 8000H and 7FFFH Digital Feedthrough 2 nV-s typ DAC Alternately Loaded with 0000H and FFFFH; CS High Output Noise Voltage 120 nV/ √Hz typ Measured at VOUT, 20 V Span; Excludes Reference Density (1 kHz – 1 MHz) Reference Noise 125 nV/ √Hz typ Measured at REF OUT Specifications subject to change without notice. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed. Those shown in boldface are tested on all production units. (With the exception of Total Harmonic Distortion + Noise and Signal-to-Noise Ratio, these characteristics are included for design guidance only and are not subject to test. THD+N and SNR are 100% tested. TMIN ≤ T A ≤ T MAX, VCC = +15 V, VEE = –15 V, VLL = +5 V except where noted.) DATA LDAC tDS tDH CS tLW t LH L1 t CS t L1 Figure 1a. AD669 Level Triggered Timing Diagram DATA t DS tDH CS AND/OR L1, LDAC TIE CS AND/OR L1 TO GROUND OR TOGETHER WITH LDAC t LOW tHIGH Figure 1b. AD669 Edge Triggered Timing Diagram |
类似零件编号 - AD669AN |
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类似说明 - AD669AN |
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