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CS1612 数据表(PDF) 8 Page - Cirrus Logic |
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CS1612 数据表(HTML) 8 Page - Cirrus Logic |
8 / 17 page CS1610/11/12/13 8 DS929F5 5. GENERAL DESCRIPTION 5.1 Overview The CS1610/11/12/13 is a digital control IC engineered to deliver a high-efficiency, cost-effective, flicker-free, phase- dimmable, solid-state lighting (SSL) solution for the incandescent lamp replacement market. The CS1610/11 is designed to control a quasi-resonant flyback topology. The CS1612/13 is designed to control a buck topology. The CS1610/12 and CS1611/13 are designed for 120VAC and 230VAC line voltage applications, respectively. The CS1610/11/12/13 integrates a critical conduction mode (CRM) boost converter that provides power factor correction and dimmer compatibility with a constant output current, quasi- resonant second stage. An adaptive dimmer compatibility algorithm controls the boost stage and dimmer compatibility operation mode to enable flicker-free operation to <2% output current with leading-edge, trailing-edge, and digital dimmers (dimmers with an integrated power supply). 5.2 Startup Circuit An external, high-voltage source-follower circuit is used to deliver startup current to the IC. During steady-state operation, an auxiliary winding on the boost inductor biases this circuit to an off state to improve system efficiency, and all IC supply current is generated from the auxiliary winding. The patent- pending technology of the external, high-voltage source- follower circuit enables system compatibility with digital dimmers (dimmers containing an internal power supply) by providing a continuous path for the dimmer’s power supply to recharge during its off state. During steady-state operation, the high-voltage FET, Q2, in this circuit is source-switched by a variable internal current source on the SOURCE pin to create the boost circuit. A Schottky diode with a forward voltage less than 0.6V is recommended for D5. Schottky diode D5 will limit inrush current through the internal diode preventing damage to the IC. 5.3 Dimmer Switch Detection The CS1610/11/12/13 dimmer switch detection algorithm determines if the SSL system is controlled by a regular switch, a leading-edge dimmer, or a trailing-edge dimmer. Dimmer switch detection is implemented using two modes: Dimmer Learn Mode and Dimmer Validate Mode. These assist in limiting the system power losses. Once the IC reaches its UVLO start threshold, VST(th), and begins operating, the CS1610/11/12/13 is in Dimmer Learn Mode, allowing the dimmer switch detection circuit to set the operating state of the IC to one of three modes: No-dimmer Mode, Leading-edge Mode, or Trailing-edge Mode. 5.3.1 Dimmer Learn Mode In Dimmer Learn Mode, the dimmer detection circuit spends approximately two line-cycles learning whether there is a dimmer switch and, if present, whether it is a trailing-edge or leading-edge dimmer. In Dimmer Learn Mode, a modified version of the leading-edge algorithm is used. The trailing-side slope of the input line voltage is sensed to decide whether the dimmer switch is a trailing-edge dimmer. The dimmer detection circuit transitions to Dimmer Validate Mode once the circuit detects a dimmer is present. 5.3.2 Dimmer Validate Mode During normal operation, CS1610/11/12/13 is in Dimmer Validate Mode. This instructs the dimmer detection circuit to periodically validate that the IC is executing the correct algorithm for the attached dimmer. The dimmer detection algorithm periodically verifies the IC operating state as a protection against incorrect detection. As additional protection, the output of the dimmer detection algorithm is low-pass filtered to prevent noise or transient events from changing the IC’s operating mode. The IC will return to Dimmer Learn Mode when it has determined that the wrong algorithm is being executed. 5.3.3 No-dimmer Mode Upon detection that the line is not phase cut with a dimmer, the CS1610, CS1610-01, and CS1611/12/13 operates in No- dimmer Mode, where it provides a power factor that is in excess of 0.9. The CS1610-01 and CS1611/12/13 accomplishes this by boosting in CRM and DCM mode. The CS1610 boosts in CRM mode only. The peak current is modulated to provide link regulation. The CS1610/11/12/13 alternates between two settings of peak current. To regulate the boost output voltage, the device uses a peak current set by the RIPK resistor. The time that this current is used is determined by an internal compensation loop to regulate the boost output voltage. The internal algorithm will reduce the peak current of the boost stage to maintain output voltage regulation and obtain the desired power factor. 5.3.4 Leading-edge Mode In Leading-edge Mode, the CS1610/11/12/13 regulates the link voltage while maintaining the dimmer phase angle. To accomplish this, the CS1610/11/12/13 uses CCM boosting with dimmer attach current as the initial peak current on the initial firing event of the dimmer. After gaining control of the incoming current, the CS1610/11/12/13 transitions to a CRM boost algorithm to regulate the link voltage. The CS1610/11/12/13 periodically executes a probe event on the incoming waveform. The information from the probe event is beneficial to maintaining proper operation with the dimmer circuitry. 5.3.5 Trailing-edge Mode In Trailing-edge Mode, the CS1610/11/12/13 determines its operation based on the falling edge of the input voltage waveform. To allow the dimmer to operate properly, the CS1610/11/12/13 must charge the capacitor in the dimmer on the falling edge of the input voltage. To accomplish this, the CS1610/11/12/13 always executes the boost algorithm on this falling edge. To ensure maximum compatibility with dimmer components, the device boosts during this falling edge event using a peak current that must meet a minimum value. In Trailing-edge Mode, only CRM boosting is used. |
类似零件编号 - CS1612 |
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类似说明 - CS1612 |
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