AD654

REV. B

–9–

8

7

6

5

1

2

3

4

AD654

1k

(0V TO 1V)

1000pF

5V

10k

825

1%

500

A

D

+

–

6MHz

20pF

20pF

1 F

XTAL1

XTAL2

RESET

EA

SS

INT

T0

T1

P10

P17

P20

P27

DB0

DB7

PORT 1

PORT 2

BUS

PORT

5V

GND

ALE

PSEN PROG WR RD

8048

NC

NC

NC

NC = NO CONNECT

Figure 11. AD654 VFC as an ADC

FREQUENCY DOUBLING

Since the AD654’s output is a square-wave rather than a pulse

train, information about the input signal is carried on both

halves of the output waveform. The circuit in Figure 12 converts

the output into a pulse train, effectively doubling the output

frequency, while preserving the better low frequency linearity of

the AD654. This circuit also accommodates an input voltage

that is greater than the AD654 supply voltage.

Resistors R1–R3 are used to scale the 0 V to +10 V input voltage

down to 0 V to +1 V as seen at Pin 4 of the AD654. Recall that

The timing resistor and capacitor are selected such that this 0 V

to +1 V signal seen at Pin 4 results in a 0 kHz to 200 kHz output

frequency.

The use of R4, C1 and the XOR gate doubles this 200 kHz

output frequency to 400 kHz. The AD654 output transistor is

basically used as a switch, switching capacitor C1 between a

charging mode and a discharging mode of operation. The voltages

seen at the input of the 74LS86 are shown in the waveform dia-

gram. Due to the difference in the charge and discharge time

constants, the output pulse widths of the 74LS86 are not equal.

The output pulse is wider when the capacitor is charging due to

its longer rise time than fall time. The pulses should therefore be

counted on their rising, rather than falling, edges.

AD654

1k

500pF

2.87k

R3

1k

R2

2k

R1

8.06k

C1

1000pF

R4

1k

5V

A

B

C

74LS86

(0V TO 10V)

V/F OUTPUT

FS = 400MHz

OFF

ON

V

0

V

0

5

0

TRANSISTOR

A

B

C

WAVEFORM DIAGRAM

OSC/

DRIVER

Figure 12. Frequency Doubler