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AD5551BR 数据表(PDF) 11 Page - Analog Devices |
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AD5551BR 数据表(HTML) 11 Page - Analog Devices |
11 / 12 page AD5551/AD5552 –11– REV. 0 The 80C51/80L51 provides the LSB first, while the AD5551/ AD5552 expects the MSB of the 14-bit word first. Care should be taken to ensure the transmit routine takes this into account. Usually it can be done through software by shifting out and accu- mulating the bits in the correct order before inputting to the DAC. Also, 80C51 outputs 2 byte words/16 bits data, thus the first two bits, after rearrangement, should be DON’T CARE as they will be dropped from the DAC’s 14-bit word. When data is to be transmitted to the DAC, P3.3 is taken low. Data on RxD is valid on the falling edge of TxD, so the clock must be inverted as the DAC clocks data into the input shift register on the rising edge of the serial clock. The 80C51/80L51 transmits its data in 8-bit bytes with only eight falling clock edges occur- ring in the transmit cycle. As the DAC requires a 14-bit word, P3.3 (or any one of the other programmable bits) is the CS input signal to the DAC, so P3.3 should be brought low at the begin- ning of the 16-bit write cycle 2 × 8 bit words and held low until the 16-bit 2 × 8 cycle is completed. After that, P3.3 is brought high again and the new data loads to the DAC. Again, the first two bits, after rearranging, should be DON’T CARE. LDAC on the AD5552 may also be controlled by the 80C51/80L51 serial port output by using another bit programmable pin, P3.4. APPLICATIONS Optocoupler interface The digital inputs of the AD5551/AD5552 are Schmitt- triggered, so they can accept slow transitions on the digital input lines. This makes these parts ideal for industrial applications where it may be necessary that the DAC is isolated from the controller via optocouplers. Figure 9 illustrates such an interface. SCLK DIN CS AD5551/AD5552 DIN CS SCLK VDD POWER 5V REGULATOR GND 10 F 10k VOUT 10k 10k 0.1 F VDD VDD VDD Figure 9. AD5551/AD5552 in an Optocoupler Interface Decoding Multiple AD5551/AD5552s The CS pin of the AD5551/AD5552 can be used to select one of a number of DACs. All devices receive the same serial clock and serial data, but only one device will receive the CS signal at any one time. The DAC addressed will be determined by the decoder. There will be some digital feedthrough from the digital input lines. Using a burst clock will minimize the effects of digi- tal feedthrough on the analog signal channels. Figure 10 shows a typical circuit. ENABLE DIN SCLK DGND CODED ADDRESS DECODER VDD EN AD5551/AD5552 CS DIN SCLK VOUT AD5551/AD5552 CS DIN SCLK VOUT AD5551/AD5552 CS DIN SCLK VOUT AD5551/AD5552 CS DIN SCLK VOUT Figure 10. Addressing Multiple AD5551/AD5552s |
类似零件编号 - AD5551BR |
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类似说明 - AD5551BR |
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