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AD5327 数据表(PDF) 6 Page - Analog Devices |
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AD5327 数据表(HTML) 6 Page - Analog Devices |
6 / 20 page REV. F –6– AD5305/AD5315/AD5325 PIN CONFIGURATION TOP VIEW (Not to Scale) 10 9 8 7 6 1 2 3 4 5 VDD VOUTA GND SDA SCL VOUTD AD5305/ AD5315/ AD5325 VOUTB VOUTC REFIN A0 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1VDD Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled to GND. 2VOUTABuffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 3VOUTBBuffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 4VOUTCBuffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. 5 REFIN Reference Input Pin for All Four DACs. It has an input range from 0.25 V to VDD. 6VOUTDBuffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. 7GND Ground Reference Point for All Circuitry on the Part. 8 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input shift register. It is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor. 9 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input shift register. Clock rates of up to 400 kbit/s can be accommodated in the 2-wire interface. 10 A0 Address Input. Sets the least significant bit of the 7-bit slave address. TERMINOLOGY Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSB, from a straight line passing through the endpoints of the DAC transfer function. Typical INL versus code plots can be seen in TPCs 1, 2, and 3. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL versus code plots can be seen in TPCs 4, 5, and 6. Offset Error This is a measure of the offset error of the DAC and the output amplifier. It is expressed as a percentage of the full-scale range. Gain Error This is a measure of the span error of the DAC. It is the devia- tion in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range. Offset Error Drift This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/ °C. Gain Error Drift This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/ °C. Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dB. VREF is held at 2 V and VDD is varied ±10%. DC Crosstalk This is the dc change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of another DAC. It is expressed in µV. Reference Feedthrough This is the ratio of the amplitude of the signal at the DAC out- put to the reference input when the DAC output is not being updated. It is expressed in dB. |
类似零件编号 - AD5327 |
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类似说明 - AD5327 |
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