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AD53042 数据表(PDF) 2 Page - Analog Devices

部件名 AD53042
功能描述  High Speed Window Comparator
Download  4 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD53042 数据表(HTML) 2 Page - Analog Devices

  AD53042 Datasheet HTML 1Page - Analog Devices AD53042 Datasheet HTML 2Page - Analog Devices AD53042 Datasheet HTML 3Page - Analog Devices AD53042 Datasheet HTML 4Page - Analog Devices  
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–2–
REV. A
AD53042–SPECIFICATIONS
(All specifications apply with TC = 40 C to 100 C and +VS = +7.75 V to +11.5 V;
–VS = –3.95 V to –7.7 V unless otherwise noted.)
Parameter
Min
Typ
Max
Units
Test Conditions
POWER SUPPLIES
Positive Supply Currents
65
mA
No Load
Negative Supply Current
–85
mA
No Load
Power Dissipation
1.19
W
No Load, +VS = +10 V, –VS = –5.2 V
DC INPUT CHARACTERISTICS
Offset Voltage (VOS)
–10
10
mV
CMV = 0 V
VIN Bias Current
–0.5
<0.1
0.5
µAV
IN = 0 V
VA, VB Bias Current
–20
20
µAV
IN = 0 V
Capacitance VIN, VA, VB
2pF
Voltage Range (VCM)–VS + 2.7
+VS – 2.5
V
Differential Voltage (VDIFF)9
V
Nonlinearity
–5
5
mV
See Note 1
VA/VB Interaction
0.1
mV/V
BIAS CURRENT
Change vs. Comparator State
–1
1
µA
Nonlinearity
–2
2
µA
Tempco
±0.1
µA/°C
LATCH ENABLE INPUTS
Common-Mode Range
–2
1
V
Differential Voltage
0.4
3
V
Logic “1” Current (LIH)
200
µA
Logic “0” Current (LIL)
–10
µA
DIGITAL OUTPUTS
Logic “1” Voltage (VOH)
–0.98
V
Q or
Q, 50
Ω to –2 V
Logic “0” Voltage (VOL)
–1.5
V
Q or
Q, 50
Ω to –2 V
SWITCHING PERFORMANCE
Propagation Delay
Input to Output
2
ns
VIN = 2 V p-p, tPDR, tPDF, Figure 1, Note 2
Latch Enable to Output
1.2
ns
Part-to-Part Skew
1
ns
Change vs. Temperature
±1
ps/
°C
DISPERSION
5 V p-p Input (All Edges)
±100
ps
10%, 90% 0.5 V/ns, 3 V/ns
5 V p-p Input (All Edges)
±175
ps
10%, 90% 5 V/ns
V Slew = 1 V/ns (All Edges)
±50
ps
10%, 90% 3 V, 5 V
V Slew = 1 V/ns (All Edges)
±50
ps
20%, 80% 1 V
Minimum Pulsewidth
<1
ns
See Note 3
Edge Interaction
<200
ps
See Note 4
Duty Ratio
<100
ps
See Note 5
Comparator Interaction
<100
ps
NOTES
1Defined as change in V
OS from –VS + 2.95 V to +VS – 2.75 V (throughout the range) after V A and VB are corrected for gain and offset using 0 V and 5 V.
2Propagation delay is measured from the input threshold crossing at the 50% point of a 0 V to 5 V input to the output Q and
Q crossing.
3The minimum input pulsewidth that will maintain a 600 mV ECL swing on the output. The input is a 0 V to 3 V signal with a 3 V/ns rise and fall times. The input
pulsewidth is measured between the 2.8 V point of a positive input pulse and the 0.2 V of a negative input pulse. See Figure 2.
4Maximum Change in propagation delay as the input pulse is reduced from 50 ns to a 2 ns pulsewidth. 0 V to 3 V swing with 3 V/ns rise/fall time and 25% duty cycle.
5Maximum Change in propagation delay as the input pulse is reduced from 99% to a 1% duty cycle. 0 V to 3 V swing with 3 V/ns rise/fall time and 50 ns to 4.95
µs
pulsewidth, period = 5
µs.
Specifications subject to change without notice.


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