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AD8400 数据表(PDF) 6 Page - Analog Devices |
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AD8400 数据表(HTML) 6 Page - Analog Devices |
6 / 20 page REV. 0 –6– AD5232 PIN FUNCTION DESCRIPTIONS Pin Number Mnemonic Description 1 CLK Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges. 2 SDI Serial Data Input Pin. MSB Loaded First. 3 SDO Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands 9 and 10 activate the SDO output. See Table II. Other commands shift out the previously loaded SDI bit pattern delayed by 16 clock pulses. This allows daisy-chain operation of multiple packages. 4 GND Ground Pin, Logic Ground Reference. 5VSS Negative Supply. Connect to zero volts for single supply applications. 6 A1 A Terminal of RDAC1 7 W1 Wiper Terminal of RDAC1, ADDR(RDAC1) = 0H 8 B1 B Terminal of RDAC1 9 B2 B Terminal of RDAC2 10 W2 Wiper Terminal of RDAC2, ADDR(RDAC2) = 1H 11 A2 A Terminal of RDAC2 12 VDD Positive Power Supply Pin 13 WP Write Protect Pin. When active low, WP prevents any changes to the present register contents, except PR and CMD 1 and 8 will refresh RDAC register from EEMEM. Execute a NOP instruction before returning WP to logic high. 14 PR Hardware Override Preset Pin. Refreshes the scratch pad register with current contents of the EEMEM register. Factory default loads midscale 80H until EEMEM is loaded with a new value by the user ( PR is activated at the logic high transition). 15 CS Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high. 16 RDY Ready. Active-high open drain output, requires pull-up resistor. Identifies completion of commands 2, 3, 8, 9, 10, and PR. TOP VIEW (Not to Scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 CLK SDI SDO GND VSS A1 W1 B1 RDY CS PR WP VDD A2 W2 B2 AD5232 PIN CONFIGURATION |
类似零件编号 - AD8400 |
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类似说明 - AD8400 |
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