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FM28V100-TGTR 数据表(PDF) 7 Page - Cypress Semiconductor

部件名 FM28V100-TGTR
功能描述  1Mbit Bytewide F-RAM Memory
Download  13 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

FM28V100-TGTR 数据表(HTML) 7 Page - Cypress Semiconductor

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FM28V100 - 128Kx8 FRAM
Rev. 3.0
Apr. 2012
Page 7 of 13
Electrical Specifications
Absolute Maximum Ratings
Symbol
Description
Ratings
VDD
Power Supply Voltage with respect to VSS
-1.0V to +4.5V
VIN
Voltage on any signal pin with respect to VSS
-1.0V to +4.5V and
VIN < VDD+1V
TSTG
Storage Temperature
-55C to +125C
TLEAD
Lead Temperature (Soldering, 10 seconds)
260 C
VESD
Electrostatic Discharge Voltage
- Human Body Model (AEC-Q100-002 Rev. E)
- Charged Device Model (AEC-Q100-011 Rev. B)
- Machine Model (AEC-Q100-003 Rev. E)
2kV
1.25kV
200V
Package Moisture Sensitivity Level
MSL-3
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40 C to +85 C, VDD = 2.0V to 3.6V unless otherwise specified)
Symbol
Parameter
Min
Typ
Max
Units
Notes
VDD
Power Supply
2.0
3.3
3.6
V
IDD
VDD Supply Current
7
12
mA
1
ISB
Standby Current – CMOS
90
150
A
2
ILI
Input Leakage Current
1
A
3
ILO
Output Leakage Current
1
A
3
VIH
Input High Voltage
0.7 VDD
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0.3 VDD
V
VOH1
Output High Voltage (IOH = -1 mA, VDD=2.7V)
2.4
V
VOH2
Output High Voltage (IOH = -100 A)
VDD-0.2
V
VOL1
Output Low Voltage (IOL = 2 mA, VDD=2.7V)
0.4
V
VOL2
Output Low Voltage (IOL = 150 A)
0.2
V
RIN
Address Input Resistance (CE2)
For VIN = VIH (min)
For VIN = VIL (max)
40
1
K
M
4
Notes
1.
VDD = 3.6V, CE cycling at minimum cycle time. All inputs at CMOS levels (0.2V or VDD-0.2V), all DQ pins unloaded.
2.
VDD = 3.6V, /CE1 at VDD or CE2 at VSS, and all other pins at CMOS levels (0.2V or VDD-0.2V).
3.
VIN, VOUT between VDD and VSS.
4.
The input pull-up circuit is stronger (>40K) when the input voltage is above VIH and weak (>1M) when the input
voltage is below VIL.


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