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FIN3385MTDX 数据表(PDF) 11 Page - Fairchild Semiconductor |
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FIN3385MTDX 数据表(HTML) 11 Page - Fairchild Semiconductor |
11 / 21 page © 2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN3385 / FIN3386 • Rev. 1.0.6 11 Receiver AC Characteristics Typical values are at TA=25°C and with VCC=3.3V; minimum and maximum are at over supply voltages and operating temperatures ranges, unless otherwise specified. Symbol Parameter Condition Min. Typ. Max. Unit tRCOP Receiver Clock Output (RxCLKOut) Period Figure 12 Rising Edge Strobe f=85MHz 11.76 T 50.00 tRCOL RxCLKOut LOW Time 4.0 5.0 6.0 ns tRCOH RxCLKOut HIGH Time 4.5 5.0 6.5 ns tRSRC RxOut Valid Prior to RxCLKOut 3.5 ns tRHRC RxOut Valid After RxCLKOut 3.5 ns tROLH Output Rise Time (20% to 80%) CL=8pF, Figure 8 2.0 3.5 ns tROHL Output Fall Time (80% to 20%) 1.8 3.5 tRCCD Receiver Clock Input to Clock Output Delay (15) TA=25°C, VCC=3.3V, Figure 24 3.5 5.0 7.5 ns tRPPD Receiver Power-Down Delay Figure 17 1.0 µs tRSPB0 Receiver Input Strobe Position of Bit 0 Figure 21 f=85MHz 0.49 0.84 1.19 ns tRSPB1 Receiver Input Strobe Position of Bit 1 2.17 2.52 2.87 ns tRSPB2 Receiver Input Strobe Position of Bit 2 3.85 4.20 4.55 ns tRSPB3 Receiver Input Strobe Position of Bit 3 5.53 5.88 6.23 ns tRSPB4 Receiver Input Strobe Position of Bit 4 7.21 7.56 7.91 ns tRSPB5 Receiver Input Strobe Position of Bit 5 8.89 9.24 9.59 ns tRSPB6 Receiver Input Strobe Position of Bit 6 10.57 10.92 11.27 ns tRSKM RxIN Skew Margin (16) Figure 21 290 ps tRPLLS Receiver Phase Lock Loop Set Time Figure 21 10 ms tRCOP Receiver Clock Output (RxCLKOut) Period Figure 12 15 T 50 ns tRCOL RxCLKOut LOW Time Figure 12 Rising Edge Strobe f=40MHz 10.0 11.0 ns tRCOH RxCLKOut HIGH Time 10.0 12.2 tRSRC RxOUT Valid Prior to RxCLKOut 6.5 11.6 tRHRC RxOUT Valid After RxCLKOut 6.0 11.6 tRCOL RxCLKOut LOW Time Figure 12, Rising Edge Strobe (17) f=66MHz 5.0 6.3 9.0 ns tRCOH RxCLKOut HIGH Time 5.0 7.6 9.0 tRSRC RxOUT Valid Prior to RxCLKOut 4.5 7.3 tRHRC RxOUT Valid After RxCLKOut 4.0 6.3 tROLH Output Rise Time (20% to 80%) CL=8pF (17), Figure 12 2.0 5.0 ns tROHL Output Fall Time (20% to 80%) 1.8 5.0 tRCCD Receiver Clock Input to Clock Output Delay (18) Figure 14, TA=25°C and VCC=3.3v 3.5 5.0 7.5 ns tRPDD Receiver Power-Down Delay Figure 17 1.0 µs tRSPB0 Receiver Input Strobe Position of Bit 0 Figure 21, f=40MHz 1.00 1.40 2.15 ns tRSPB1 Receiver Input Strobe Position of Bit 1 4.50 5.00 5.80 tRSPB2 Receiver Input Strobe Position of Bit 2 8.10 8.50 9.15 tRSPB3 Receiver Input Strobe Position of Bit 3 11.6 11.9 12.6 tRSPB4 Receiver Input Strobe Position of Bit 4 15.1 15.6 16.3 tRSPB5 Receiver Input Strobe Position of Bit 5 18.8 19.2 19.9 tRSPB6 Receiver Input Strobe Position of Bit 6 22.5 22.9 23.6 |
类似零件编号 - FIN3385MTDX |
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类似说明 - FIN3385MTDX |
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