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FIN425CMLX 数据表(PDF) 2 Page - Fairchild Semiconductor |
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FIN425CMLX 数据表(HTML) 2 Page - Fairchild Semiconductor |
2 / 10 page © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN424C / FIN425C • Rev. 1.0.0 2 FIN424C Serializer Pin Descriptions Pin Name Description STRB LVCMOS Strobe Signal for Latching Data into the Serializer (On Rising Edge) DP[19:0] LVCMOS Data Input /RES Low-Power Mode 0 Serializer Low Power 1 Serializer Enabled /STBY SerDes Standby 0 Serializer and Deserializer in Low Power 1 Serializer and Deserializer Enabled Test Internal Use (Should be GND) DS+, DS- Serial Data Output CKS+, CKS- Serial Clock Output VDDP Power Supply for Parallel I/O and Internal Circuitry VDDS Power Supply for Serial I/O VDDA Power Supply for Core GND Ground Pins Notes: 1. 0 = VIL; 1 = VIH. 2. All GND and VDDP pins must be connected to ground and VDDP, respectively. GND PAD Must be Grounded CKS+ DP[12] DP[11] DP[10] VDDP DP[9] DP[8] DP[7] DP[6] 1 CKS- 2 4 VDDS VDDA 3 DS- 5 DS+ 6 /RES 7 VDDP 8 20 21 19 23 18 17 22 24 GND PAD Must be Grounded CKS+ DP[12] DP[11] DP[10] VDDP DP[9] DP[8] DP[7] DP[6] 1 CKS- 2 4 VDDS VDDA 3 DS- 5 DS+ 6 /RES 7 VDDP 8 20 21 19 23 18 17 22 24 Figure 2. FIN424CMLX MLP-32 Pinout (Top Through View) |
类似零件编号 - FIN425CMLX |
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类似说明 - FIN425CMLX |
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