TS7003

TS7003DS r1p0

Page 11

RTFDS

Figure 8: TS7003 Serial Interface Timing Sequence

Figure 9: TS7003 Serial Interface Timing Specifications in Detail.

APPLICATIONS INFORMATION

Connection to Industry-Standard Serial Interfaces

The TS7003

’s serial interface is fully compatible with

SPI/QSPI

and

MICROWIRE

standard

serial

interfaces (Refer to Figure 11). For serial interface

operation with these standards, the CPU’s serial

interface should be set to master mode so the CPU

then generates the serial clock. Second, the CPU’s

serial clock should be configured to operate up to

4.8MHz. The process to configure the serial clock and

data transfer operation is as follows:

1) Using a general-purpose I/O line from the CPU, the

CS pin is driven low to start a conversion. DOUT

transitions from high impedance to logic low. The

SCLK polarity should be low to start the conversion

process correctly.

2) Next, SCLK is activated for a minimum of 15 SCLK

cycles where the first two SCLKs produce zeros at

the DOUT pin. Data at DOUT is formatted MSB first

and DOUT transitions occur 20ns after the third (3

SCLK low-to-high transition. Once the low-to-high

SCLK transition has occurred, data is valid at DOUT

TIME IN SHUTDOWN MODE - sec

2

1

0.5

0

0.1m

10m

1

10

100m

2.5

1.5

1m

Figure 7: TS7003 Reference Power-Up Delay

vs Duration in Shutdown Mode