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TDA7565 数据表(PDF) 10 Page - STMicroelectronics |
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TDA7565 数据表(HTML) 10 Page - STMicroelectronics |
10 / 19 page I2C bus interface TDA7565 10/19 Doc ID 9800 Rev 4 3 I2C bus interface Data transmission from microprocessor to the TDA7565 and vice versa takes place through the 2 wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 3.1 Data validity As shown by Figure 4, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 3.2 Start and stop conditions As shown by Figure 5 a start condition is a high to low transition of the SDA line while SCL is HIGH. The stop condition is a low to high transition of the SDA line while SCL is high. 3.3 Byte format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 3.4 Acknowledge The transmitter* puts a resistive high level on the SDA line during the acknowledge clock pulse (see Figure 6). The receiver** the acknowledges has to pull-down (low) the SDA line during the acknowledge clock pulse, so that the SDA line is stable low during this clock pulse. * Transmitter –master ( μP) when it writes an address to the TDA7565 – slave (TDA7565) when the μP reads a data byte from TDA7565 ** Receiver – slave (TDA7565) when the μP writes an address to the TDA7565 – master (µP) when it reads a data byte from TDA7565 Figure 4. Data validity on the I2C bus SDA SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED D99AU1031 |
类似零件编号 - TDA7565_10 |
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类似说明 - TDA7565_10 |
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