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STA381BW 数据表(PDF) 6 Page - STMicroelectronics

部件名 STA381BW
功能描述  Sound Terminal짰 2.1-channel high-efficiency digital audio system
Download  171 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA381BW 数据表(HTML) 6 Page - STMicroelectronics

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Contents
STA381BW
6/171
Doc ID 018835 Rev 7
6.27
PLL configuration registers
(address 0x52; 0x53; 0x54; 0x55; 0x56; 0x57) . . . . . . . . . . . . . . . . . . . . 87
6.28
Short-circuit protection mode registers SHOK (address 0x58) . . . . . . . . 89
6.29
Extended coefficient range up to -4...4 (address 0x5A) . . . . . . . . . . . . . . 90
6.30
Miscellaneous registers (address 0x5C, 0x5D) . . . . . . . . . . . . . . . . . . . . 91
6.30.1
Rate power-down enable (RPDNEN) bit . . . . . . . . . . . . . . . . . . . . . . . . 91
6.30.2
Bridge immediately off (BRIDGOFF) bit (address 0x4B, bit D5) . . . . . . 91
6.30.3
Channel PWM enable (CPWMEN) bit . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.30.4
External amplifier hardware pin enabler (LPDP, LPD LPDE) bits . . . . . 92
6.30.5
Power-down delay selector (PNDLSL[2:0]) bits . . . . . . . . . . . . . . . . . . . 92
6.30.6
Short-circuit check enable bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.31
Bad PWM detection registers (address 0x5E, 0x5F, 0x60) . . . . . . . . . . . 93
6.32
Enhanced zero-detect mute and input level measurement
(address 0x61-0x65, 0x3F, 0x40, 0x6F) . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.33
Headphone/Line out configuration register (address 0x66) . . . . . . . . . . . 96
6.34
F3XCFG (address 0x69; 0x6A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.35
STCompressorTM configuration register (address 0x6B; 0x6C) . . . . . . . 98
6.36
Charge pump synchronization (address 0x70) . . . . . . . . . . . . . . . . . . . . . 98
6.37
Coefficient RAM CRC protection (address 0x71-0x7D) . . . . . . . . . . . . . . 99
6.38
MISC4 (address 0x7E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7
Register description: Sound Terminal compatibility . . . . . . . . . . . . . 103
7.1
Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.1.1
Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.1.2
Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
7.1.3
Fault-detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
7.2
Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.2.1
Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.2.2
Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.2.3
Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.2.4
Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.2.5
Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.3
Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.3.1
FFX compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.4
Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.4.1
DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112


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