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MC14572UBDG 数据表(PDF) 1 Page - ON Semiconductor

部件名 MC14572UBDG
功能描述  Hex Gate
Download  6 Pages
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制造商  ONSEMI [ON Semiconductor]
网页  http://www.onsemi.com
标志 ONSEMI - ON Semiconductor

MC14572UBDG 数据表(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 7
1
Publication Order Number:
MC14572UB/D
MC14572UB
Hex Gate
The MC14572UB hex functional gate is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. These complementary MOS logic gates find
primary use where low power dissipation and/or high noise immunity
is desired. The chip contains four inverters, one NOR gate and one
NAND gate.
Features
Diode Protection on All Inputs
Single Supply Operation
Supply Voltage Range = 3.0 Vdc to 18 Vdc
NOR Input Pin Adjacent to VSS Pin to Simplify Use As An Inverter
NAND Input Pin Adjacent to VDD Pin to Simplify Use As An
Inverter
NOR Output Pin Adjacent to Inverter Input Pin For OR Application
NAND Output Pin Adjacent to Inverter Input Pin For AND
Application
Capable of Driving Two Low−Power TTL Loads or One
Low−Power Schottky TTL Load over the Rated Temperature
Range
These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
VDD
−0.5 to +18.0
V
Input or Output Voltage Range
(DC or Transient)
Vin, Vout
−0.5 to VDD
+ 0.5
V
Input or Output Current (DC or Transient)
per Pin
Iin, Iout
±10
mA
Power Dissipation, per Package (Note 1)
PD
500
mW
Ambient Temperature Range
TA
−55 to +125
°C
Storage Temperature Range
Tstg
−65 to +150
°C
Lead Temperature (8−Second Soldering)
TL
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
Device
Package
Shipping
ORDERING INFORMATION
http://onsemi.com
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
MC14572UBDR2G
SOIC−16
(Pb−Free)
2500/Tape & Reel
MC14572UBDG
SOIC−16
(Pb−Free)
48 Units / Rail
MC14572UBCPG
PDIP−16
(Pb−Free)
25 Units / Rail
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
SOIC−16
D SUFFIX
CASE 751B
1
16
14572UBG
AWLYWW
16
1
MC14572UBCP
AWLYYWWG
1
1


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