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SN74ACT72231L35RJ 数据表(PDF) 5 Page - Texas Instruments |
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SN74ACT72231L35RJ 数据表(HTML) 5 Page - Texas Instruments |
5 / 21 page SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L 512 × 9, 1024 × 9, 2048 × 9, AND 4096 × 9 SYNCHRONOUS FIRST IN, FIRST OUT MEMORIES SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 flag programming (continued) The contents of the offset registers can be read to the data outputs when WEN2/LD is low and both REN1 and REN2 are low. Low-to-high transitions of RCLK read the register contents to the data outputs. Writes and reads should not be performed simultaneously on the offset registers (see Figure 1 and Table 1). Empty Offset (LSB) Register Default Value = 007h SN74ACT72211L − 512 × 9-Bit 87 0 81 0 (MSB) 0 Full Offset (LSB) Register Default Value = 007h 87 0 81 0 (MSB) 0 Empty Offset (LSB) Register Default Value = 007h SN74ACT72221L − 1024 × 9-Bit 87 0 81 0 (MSB) 00 Full Offset (LSB) Register Default Value = 007h 87 0 81 0 (MSB) 00 Empty Offset (LSB) Register Default Value = 007h SN74ACT72231L − 2048 × 9-Bit 87 0 82 0 (MSB) 000 Full Offset (LSB) Register Default Value = 007h 87 0 82 0 (MSB) 000 Empty Offset (LSB) Register Default Value = 007h SN74ACT72241L − 4096 × 9-Bit 87 0 83 0 (MSB) 0000 Full Offset (LSB) Register Default Value = 007h 87 0 83 0 (MSB) 0000 Figure 1. Offset Register Location and Default Values |
类似零件编号 - SN74ACT72231L35RJ |
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类似说明 - SN74ACT72231L35RJ |
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