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SN74ALVC16901 数据表(PDF) 3 Page - Texas Instruments |
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SN74ALVC16901 数据表(HTML) 3 Page - Texas Instruments |
3 / 9 page SN74ALVC16901 18BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCAS276A − NOVEMBER 1993 − REVISED JULY 1995 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PARITY-ENABLE FUNCTION TABLE INPUTS OPERATION OR FUNCTION SEL OEBA OEAB OPERATION OR FUNCTION L H L Parity is checked on port A and is generated on port B. L L H Parity is checked on port B and is generated on port A. L H H Parity is checked on port B and port A. L L L Parity is generated on port A and B if device is in FF mode. H L L Parity functions are QA data to B, QB data to A H LH Parity functions are disabled; device acts as a QB data to A H HL disabled; device acts as a standard 18-bit registered transceiver. QA data to B H H H standard 18-bit registered transceiver. Isolation PARITY FUNCTION TABLE INPUTS OUTPUTS SEL OEBA OEAB ODD/EVEN Σ OF INPUTS A1 − A8 = H Σ OF INPUTS B1 − B8 = H APAR BPAR APAR ERRA BPAR ERRB L H L L 0, 2, 4, 6, 8 N/A L N/A N/A H L Z L H L L 1, 3, 5, 7 N/A L N/A N/A LH Z L H L L 0, 2, 4, 6, 8 N/A H N/A N/A LL Z L H L L 1, 3, 5, 7 N/A H N/A N/A HH Z L L H L N/A 0, 2, 4, 6, 8 N/A L L Z N/A H L L H L N/A 1, 3, 5, 7 N/A L H Z N/A L L L H L N/A 0, 2, 4, 6, 8 N/A H L Z N/A L L L H L N/A 1, 3, 5, 7 N/A H H Z N/A H L H L H 0, 2, 4, 6, 8 N/A L N/A N/A L H Z L H L H 1, 3, 5, 7 N/A L N/A N/A HL Z L H L H 0, 2, 4, 6, 8 N/A H N/A N/A HH Z L H L H 1, 3, 5, 7 N/A H N/A N/A LL Z L L H H N/A 0, 2, 4, 6, 8 N/A L H Z N/A L L L H H N/A 1, 3, 5, 7 N/A L L Z N/A H L L H H N/A 0, 2, 4, 6, 8 N/A H H Z N/A H L L H H N/A 1, 3, 5, 7 N/A H L Z N/A L L H H L 0, 2, 4, 6, 8 0, 2, 4, 6, 8 L L Z H Z H L H H L 1, 3, 5, 7 1, 3, 5, 7 L L Z LZ L L H H L 0, 2, 4, 6, 8 0, 2, 4, 6, 8 H H Z LZ L L H H L 1, 3, 5, 7 1, 3, 5, 7 H H Z HZH L H H H 0, 2, 4, 6, 8 0, 2, 4, 6, 8 L L Z L Z L L H H H 1, 3, 5, 7 1, 3, 5, 7 L L Z HZH L H H H 0, 2, 4, 6, 8 0, 2, 4, 6, 8 H H Z HZH L H H H 1, 3, 5, 7 1, 3, 5, 7 H H Z LZ L L L L L N/A N/A N/A N/A PE† Z PE† Z L L L H N/A N/A N/A N/A PO‡ Z PO‡ Z † Parity output is set to the level so that the specific bus side is set to even parity. ‡ Parity output is set to the level so that the specific bus side is set to odd parity. |
类似零件编号 - SN74ALVC16901 |
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类似说明 - SN74ALVC16901 |
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