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ISL267452IHZ-T7A 数据表(PDF) 7 Page - Intersil Corporation

部件名 ISL267452IHZ-T7A
功能描述  12-Bit, 555kSPS SAR ADC
Download  16 Pages
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制造商  INTERSIL [Intersil Corporation]
网页  http://www.intersil.com/cda/home
标志 INTERSIL - Intersil Corporation

ISL267452IHZ-T7A 数据表(HTML) 7 Page - Intersil Corporation

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ISL267452
7
FN8255.0
July 26, 2012
Timing Specifications Limits established by characterization and are not production tested. VDD = 3.0V to 3.6V, fSCLK =10MHz,
fS = 555kSPS, VREF = 2.0V; VDD = 4.75V to 5.25V, fSCLK =10MHz, fS = 555kSPS, VREF =2.5V; VCM = VREF unless otherwise noted. Boldface limits apply
over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
fSCLK
Clock Frequency
0.01
10
MHz
tSCLK
Clock Period
100
ns
tACQ
Acquisition Time
200
ns
tCONV
Conversion Time
1.6
µs
tCSW
CS Pulse Width
10
ns
tCSS
CS Falling Edge to SCLK Falling Edge Setup Time
10
ns
tCDV
CS Falling Edge to SDATA Valid
20
ns
tCLKDV
SCLK Falling Edge to SDATA Valid
40
ns
tSDH
SCLK Falling Edge to SDATA Hold
10
ns
tSW
SCLK Pulse Width
0.4 x tSCLK
ns
tDISABLE
SCLK Falling Edge to SDATA Disable Time
(Note 9)
Extrapolated back to true bus relinquish
10
35
ns
tQUIET
Quiet Time Before Sample
60
ns
NOTE:
9. During characterization, tDISABLE is measured from the release point with a 10pF load (see Figure 4) and the equivalent timing using the AD7452
loading (25pF) is calculated.
FIGURE 3. SERIAL INTERFACE TIMING DIAGRAM
SCLK
SDATA
12
3
4
5
16
15
14
tCSW
tCDV
tCSS
tCONV
13
00
0
0
MSB
D0
D1
D2
tQUIET
tSW
tCLKDV
CS
HI-Z
tACQ
FIGURE 4. EQUIVALENT LOAD CIRCUIT
OUTPUT
PIN
CL
10pF
VDD
2.85k
Ω
RL


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