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ISLA224P12 数据表(PDF) 11 Page - Intersil Corporation

部件名 ISLA224P12
功能描述  High Performance Dual 14-Bit, 125MSPS ADC
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制造商  INTERSIL [Intersil Corporation]
网页  http://www.intersil.com/cda/home
标志 INTERSIL - Intersil Corporation

ISLA224P12 数据表(HTML) 11 Page - Intersil Corporation

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ISLA224P12
11
FN7983.3
August 17, 2012
FIGURE 4. CMOS
Timing Diagrams (Continued)
CLKN
CLKP
INP
INN
tA
CLKOUT
tCPD
D[13:0]
LATENCY = L CYCLES
tDC
tPD
A DATA
N-L
B DATA
N-L
A DATA
N-L+1
B DATA
N-L+1
B DATA
N-1
A DATA
N
B DATA
N
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
CONDITION
MIN
(Note 5)
TYP
MAX
(Note 5)
UNITS
ADC OUTPUT
Aperture Delay
tA
114
ps
RMS Aperture Jitter
jA
75
fs
Input Clock to Output Clock Propagation
Delay
tCPD
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
1.65
2.4
3
ns
tCPD
AVDD, OVDD = 1.8V, TA = +25°C
1.9
2.3
2.75
ns
Relative Input Clock to Output Clock
Propagation Delay (Note 13)
dtCPD
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
-450
450
ps
Input Clock to Data Propagation Delay
tPD
1.65
2.4
3.5
ns
Output Clock to Data Propagation Delay,
LVDS Mode
tDC
Rising/Falling Edge
-0.1
0.16
0.5
ns
Output Clock to Data Propagation Delay,
CMOS Mode
tDC
Rising/Falling Edge
-0.1
0.2
0.65
ns
Synchronous Clock Divider Reset Setup
Time (with Respect to the Positive Edge of
CLKP)
tRSTS
0.4
0.06
ns
Synchronous Clock Divider Reset Hold Time
(with Respect to the Positive Edge of CLKP)
tRSTH
0.02
0.35
ns
Synchronous Clock Divider Reset Recovery
Time
tRSTRT
DLL recovery time after
Synchronous Reset
52
µs
Latency (Pipeline Delay)
L
10
cycles


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