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TMP431DDGKR 数据表(PDF) 7 Page - Texas Instruments

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部件名 TMP431DDGKR
功能描述  짹1째C TEMPERATURE SENSOR with Series-R, 管-Factor, and Automatic Beta Compensation
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TMP431DDGKR 数据表(HTML) 7 Page - Texas Instruments

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TMP431, TMP432
www.ti.com
SBOS441G – SEPTEMBER 2009 – REVISED DECEMBER 2015
Electrical Characteristics (continued)
at TA = –40°C to 125°C and V+ = 2.7 V to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
V+
Specified voltage range
2.7
5.5
V
0.0625 conversions per second, V+ = 3.3 V
35
45
μA
Eight conversions per second, V+ = 3.3 V (5)
0.7
1
mA
IQ
Quiescent current
Serial bus inactive, shutdown mode
3
10
μA
Serial bus active, fS = 400 kHz, shutdown mode
90
μA
Serial bus active, fS = 3.4 MHz, shutdown mode
350
μA
UVLO
Undervoltage lockout
2.3
2.4
2.6
V
POR
Power-on reset threshold
1.6
2.3
V
Specified temperature range
–40
125
°C
Storage temperature range
–60
130
°C
(5)
Beta correction disabled.
6.6 Timing Requirements
See
(1)
FAST MODE
HIGH-SPEED MODE
UNIT
MIN
MAX
MIN
MAX
f(SCL)
SCL operating frequency
V+
0.001
0.4
0.001
2.5
MHz
t(BUF)
Bus free time between STOP and START condition
600
160
ns
Hold time after repeated START condition.
t(HDSTA)
100
100
ns
After this period, the first clock is generated.
t(SUSTA)
Repeated START condition setup time
100
100
ns
t(SUSTO)
STOP condition setup time
100
100
ns
t(HDDAT)
Data hold time
0(2)
900
0(3)
80
ns
t(SUDAT)
Data setup time
100
25
ns
t(LOW)
SCL clock LOW period
V+
1300
265
ns
t(HIGH)
SCL clock HIGH period
600
60
ns
tFD
Data fall time
300
160
ns
300
40
tRC
Clock rise time
ns
SCLK
≤ 100 kHz
1000
tFC
Clock fall time
300
40
ns
(1)
Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not specified and not
production tested.
(2)
For cases with fall time of SCL less than 20 ns and/or the rise time or fall time of SDA less than 20 ns, the hold time should be greater
than 20 ns.
(3)
For cases with fall time of SCL less than 10 ns and/or the rise or fall time of SDA less than 10 ns, the hold time should be greater than
10 ns.
Copyright © 2009–2015, Texas Instruments Incorporated
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