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DAC1001D125 数据表(PDF) 6 Page - Integrated Device Technology |
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DAC1001D125 数据表(HTML) 6 Page - Integrated Device Technology |
6 / 25 page DAC1001D125 3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 6 of 25 Integrated Device Technology DAC1001D125 Dual 10-bit DAC, up to 125 Msps IIL LOW-level input current VIL = 0.9 V - 5 - A IIH HIGH-level input current VIH =1.3 V - 5 - A Ci input capacitance [1] -5 - pF Analog outputs: pins IOUTAP, IOUTAN, IOUTBP and IOUTBN IO(fs) full-scale output current differential outputs 2 - 20 mA VO output voltage compliance range 1- +1.25 V Ro output resistance [1] -150 - k Co output capacitance [1] -3 - pF Reference voltage input/output: pin REFIO VO(ref) reference output voltage [1] 1.21 1.26 1.31 V IO(ref) reference output current - 100 - nA Vi input voltage compliance range 1.0 - 1.26 V Ri input resistance - 1 - M Input timing; see Figure 18 fs sampling frequency - - 125 Msps tw(WRT) WRT pulse width pins WRTA, WRTB 2 - - ns tw(CLK) CLK pulse width pins CLKA, CLKB 2 - - ns th(i) input hold time 1 - - ns tsu(i) input set-up time 1.8 - - ns Output timing: pins IOUTAP, IOUTAN, IOUTBP and IOUTBN td delay time - 1 - ns tt transition time rising or falling transition (10% to 90 %or90%to 10 %) [1] -0.6 - ns ts settling time 1LSB [1] -16 - ns Static linearity INL integral non-linearity 25 C 0.1 0.13 0.18 LSB 40 C to +85 C 0.08 - 0.18 LSB DNL differential non-linearity 40 C to +85 C 0.03 0.05 0.07 LSB Static accuracy (relative to full-scale) with GAINCTRL = 0 Eoffset offset error 0.02 - +0.02 % EG gain error with external reference 1.9 1.5 +2.5 % with internal reference 2.9 2.1 +2.9 % G gain mismatch between DAC A and DAC B 0.5 0.5 +0.5 % Table 5. Characteristics …continued VDDD = VDDA = 3.3 V; AGND and DGND connected together; IO(fs) = 20 mA and Tamb = 40 C to +85 C; typical values measured at Tamb = 25 C. Symbol Parameter Conditions Min Typ Max Unit |
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