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SM65MLVD047APWR 数据表(PDF) 5 Page - Texas Instruments |
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SM65MLVD047APWR 数据表(HTML) 5 Page - Texas Instruments |
5 / 21 page SN65MLVD047A SLLS736A − JULY 2006 − REVISED MAY 2008 www.ti.com 5 SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT tpLH Propagation delay time, low-to-high-level output 1 1.5 2.4 ns tpHL Propagation delay time, high-to-low-level output 1 1.5 2.4 ns tr Differential output signal rise time 1 1.9 ns tf Differential output signal fall time See Figure 5 1 1.9 ns tsk(o) Output skew(2) See Figure 5 100 ps tsk(p) Pulse skew (|tpHL − tpLH|) 22 100 ps tsk(pp) Part-to-part skew(3) 600 ps tjit(per) Period jitter, rms (1 standard deviation)(4) See Figure 8, All data inputs 100 MHz clock input 0.2 1 ps tjit(c−c) Cycle-to-cycle jitter(4) See Figure 8, All data inputs 100 MHz clock input 5 36 ps tjit(pp) Peak-to-peak jitter(3)(5) See Figure 8, All data inputs 200 Mbps 215−1 PRBS input 46 158 ps tpZH Enable time, high-impedance-to-high-level output See Figure 6 9 ns tpZL Enable time, high-impedance-to-low-level output See Figure 6 9 ns tpHZ Disable time, high-level-to-high-impedance output See Figure 6 10 ns tpLZ Disable time, low-level-to-high-impedance output See Figure 6 10 ns (1) All typical values are at 25°C and with a 3.3-V supply voltage. (2) tsk(o), output skew is the magnitude of the time difference in propagation delay times between any specified terminals of a device. (3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. (4) Stimulus jitter has been subtracted from the measurements. (5) Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)). |
类似零件编号 - SM65MLVD047APWR |
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类似说明 - SM65MLVD047APWR |
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