FAN302UL datasheet(10/19 Pages) FAIRCHILD

部件名	FAN302UL

功能描述	PWM Controller for Low Standby Power Battery-Charger Applications

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制造商	FAIRCHILD [Fairchild Semiconductor]

网页	http://www.fairchildsemi.com

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10 / 19 page

www.fairchildsemi.com

FAN302UL • Rev. 1.0.3

10

Operational Description

Basic Control Principle

Figure 24 shows the internal PWM control circuit. The

Constant Voltage (CV) regulation is implemented in the

same way as in a conventional isolated power supply,

where the output voltage is sensed using a voltage

divider and compared with the internal 2.5V reference of

shut regulator (KA431) to generate a compensation

signal. The compensation signal is transferred to the

primary side using an opto-coupler and scaled down

through an attenuator, Av, generating VEA.V signal. Then,

the error signal VEA.V is applied to the PWM comparator

(PWM.V) to determine the duty cycle.

Meanwhile, CC regulation is implemented internally

without directly sensing output current. The output

current estimator reconstructs output current data (VCCR)

using the transformer primary-side current and diode

current discharge time. Then VCCR is compared with a

reference voltage (2.5V) by an internal error amplifier,

generating a VEA.I signal to determine duty cycle.

The two error signals, VEA.I and VEA.V, are compared with

an internal sawtooth waveform (VSAW) by PWM

comparators PWM.I and PWM.V, respectively, to

determine the duty cycle. Figure 24 shows the outputs

of two comparators (PWM.I and PWM.V) combined with

OR gate and used as a reset signal of flip-flop to

determine the MOSFET turn-off instant. Of VEA.V and

VEA.I, the lower signal determines the duty cycle, as

shown in Figure 25. During CV regulation, VEA.V

determines the duty cycle while VEA.I is saturated to

HIGH. During CC regulation mode, VEA.I determines the

duty cycle while VEA.V is saturated to HIGH.

Figure 24. Internal PWM Control Circuit

CV Regulation

CC Regulation

VSAW

VEA.I

VEA.V

PWM.V

PWM.I

OSC CLK

Gate

Figure 25.PWM Operation for CC and CV

Output Current Estimation

Figure 26 shows the key waveform of a flyback

converter operating in Discontinuous Conduction Mode

(DCM), where the secondary-side diode current reaches

zero before the next switching cycle begins. Since the

output current estimator is designed for DCM operation,

the power stage should be designed such that DCM is

guaranteed for the entire operating range. The output

current is obtained by averaging the triangular output

diode current area over a switching cycle as:

2

DIS

P

OD

AVG

PK

SS

T

N

II

I

NT

=<

>

=

⋅

(1)

where IPK is the peak value of the primary-side

current; NP and NS are the number of turns of

transformer primary side and secondary side,

respectively; tDIS is the diode current discharge time;

and tS is the switching period.

P

PK

S

N

I

N

⋅

P K

I

D

AVG

O

II

<>

=

Figure 26. Key Waveforms of DCM Flyback

Converter

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