SN74LVTH18502AEP, SN74LVTH182502AEP

3.3V ABT SCAN TEST DEVICES

WITH 18BIT UNIVERSAL BUS TRANSCEIVERS

SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

2

POST OFFICE BOX 655303

description/ordering information (continued)

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),

and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when

LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level.

Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the

B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is

similar to A-to-B data flow, but uses the OEBA, LEBA, and CLKBA inputs.

In the test mode, the normal operation of the SCOPE

 universal bus transceivers is inhibited, and the test

circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry

performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),

test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs

other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudorandom pattern

generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The B-port outputs of SN74LVTH182502A, which are designed to source or sink up to 12 mA, include 25-

Ω

series resistors to reduce overshoot and undershoot.

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1A3

1A4

1A5

GND

1A6

1A7

1A8

1A9

2A1

2A2

2A3

GND

2A4

2A5

2A6

1B4

1B5

1B6

GND

1B7

1B8

1B9

2B1

2B2

2B3

2B4

GND

2B5

2B6

2B7

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