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LD39150PU25R 数据表(PDF) 4 Page - STMicroelectronics |
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LD39150PU25R 数据表(HTML) 4 Page - STMicroelectronics |
4 / 19 page Pin configuration LD39150xx 4/19 2 Pin configuration Figure 2. Pin connections (top view for DPAK and PPAK, bottom view for DFN) DFN6 (3x3 mm) DPAK PPAK Table 2. Pin description Pin n° SYMBOL NOTE DFN PPAK DPAK 55 VSENSE/N.C. For fixed versions: to be connected with LDO output voltage pins for DFN package and not connected on PPAK ADJ For adjustable version: Error amplifier input pin for VO from 1.22 to 5.0 V 32 1 VI LDO input voltage; VI from 2.5 V to 6 V, CI = 1 µF must be located at a distance of not more than 0.5’’ from input pin. 44 3 VO LDO output voltage pins, with minimum CO = 2.2 µF needed for stability (also refer to CO vs ESR stability chart) 21 VINH Inhibit input voltage: ON MODE when VINH ≥ 2 V, OFF MODE when VINH ≤ 0.3 V (Do not leave floating, not internally pulled down/up) 1 3 2 GND Common ground 6 N.C. Not connected |
类似零件编号 - LD39150PU25R |
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类似说明 - LD39150PU25R |
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