DAC5652IPFBG4 datasheet(4/27 Pages) TI1

部件名	DAC5652IPFBG4

功能描述	DUAL, 10-BIT 275 MSPS DIGITAL-TO-ANALOG CONVERTER

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制造商	TI1 [Texas Instruments]

网页	http://www.ti.com

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DAC5652

SLAS452C – MARCH 2005 – REVISED DECEMBER 2010

www.ti.com

ABSOLUTE MAXIMUM RATINGS

over TA (unless otherwise noted)

(1)

UNIT

AVDD(2)

–0.5 V to 4 V

Supply voltage range

DVDD(3)

–0.5 V to 4 V

Voltage between AGND and DGND

–0.5 V to 0.5 V

Voltage between AVDD and DVDD

–0.5 V to 0.5 V

DA[9:0] and DB[9:0](3)

–0.5 V to DVDD + 0.5 V

MODE, SLEEP, CLKA, CLKB, WRTA, WRTB(3)

–0.5 V to DVDD + 0.5 V

Supply voltage range

IOUTA1, IOUTA2, IOUTB1, IOUTB2(2)

–1 V to AVDD + 0.5 V

EXTIO, BIASJ_A, BIASJ_B, GSET(2)

–0.5 V to AVDD + 0.5 V

Peak input current (any input)

+20 mA

Peak total input current (all inputs)

–30 mA

Operating free-air temperature range

–40°C to 85°C

Storage temperature range

–65°C to 150°C

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only and functional operation of these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

Measured with respect to AGND.

(3)

Measured with respect to DGND.

ELECTRICAL CHARACTERISTICS

over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set mode (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC Specifications

Resolution

10

Bits

DC Accuracy(1)

INL

Integral nonlinearity

–1

±0.25

1

LSB

1 LSB = IOUTFS/2

10, T

MIN to TMAX

DNL

Differential nonlinearity

–0.5

±0.16

0.5

LSB

Analog Output

Offset error

Midscale value (internal reference)

±0.05

%FSR

Offset mismatch

Midscale value (internal reference)

±0.03

%FSR

Gain error

With internal reference

±0.75

%FSR

Minimum full-scale output current(2)

2

mA

Maximum full-scale output current(2)

20

mA

Gain mismatch

With internal reference

–2

0.2

2

%FSR

Output voltage compliance range(3)

–1

1.25

V

RO

Output resistance

300

k

Ω

CO

Output capacitance

5

pF

Reference Output

Reference voltage

1.14

1.2

1.26

V

Reference output current(4)

100

nA

Reference Input

VEXTIO

Input voltage

0.1

1.25

V

RI

Input resistance

1

M

Ω

Small signal bandwidth

300

kHz

(1)

Measured differentially through 50

Ω to AGND.

(2)

Nominal full-scale current, IOUTFS, equals 32x the IBIAS current.

(3)

The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,

resulting in reduced reliability of the DAC5652 device. The upper limit of the output compliance is determined by the load resistors and

full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.

(4)

Use an external buffer amplifier with high-impedance input to drive any external load.

4

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