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ADV7181D 数据表(PDF) 10 Page - Analog Devices |
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ADV7181D 数据表(HTML) 10 Page - Analog Devices |
10 / 24 page ADV7181D Data Sheet Rev. 0 | Page 10 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 47 AIN8 46 AIN7 45 AIN6 42 REFOUT 43 CML 44 CAPC2 48 AIN9 41 AVDD 40 CAPY2 39 CAPY1 37 AIN4 36 AIN3 35 AIN2 34 AIN1 33 SOG 38 AIN5 2 HS/CS 3 GND 4 DVDDIO 7 P13 6 P14 5 P15 1 INT 8 P12 9 SFL/SYNC_OUT 10 GND 12 P11 13 P10 14 P9 15 P8 16 P7 11 DVDDIO 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIN 1 ADV7181D TOP VIEW (Not to Scale) NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO GND. Figure 6. Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Type Description 1 INT Output Interrupt. This pin can be active low or active high. When SDP/CP status bits change, this pin is triggered. The set of events that triggers an interrupt is under user control. 2 HS/CS Output Horizontal Synchronization Output Signal (HS). Available in SDP and CP modes. Digital Composite Synchronization Signal (CS). Available in CP mode only. 3, 10, 24, 57 GND Ground Ground. 4, 11 DVDDIO Power Digital I/O Supply Voltage (3.3 V). 28 to 25, 19 to 12, 8 to 5, 62 to 59 P0 to P19 Output Video Pixel Output Port. See Table 10 and Table 11 for output configuration modes. 9 SFL/SYNC_OUT Output Subcarrier Frequency Lock (SFL). This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder. Sliced Synchronization Output Signal (SYNC_OUT). Available in CP mode only. 20 LLC Output Line-Locked Clock Output for Pixel Data. The range is 12.825 MHz to 75 MHz. 21 XTAL1 Output This pin should be connected to the 28.63636 MHz crystal or left unconnected if an external 3.3 V, 28.63636 MHz clock oscillator source is used to clock the ADV7181D. In crystal mode, the crystal must be a fundamental crystal. 22 XTAL Input Input Pin for the 28.63636 MHz Crystal. This input can be overdriven by an external 3.3 V, 28.63636 MHz clock oscillator source to clock the ADV7181D. 23, 58 DVDD Power Digital Core Supply Voltage (1.8 V). 29 PWRDWN Input Power-Down Input. A Logic 0 on this pin places the ADV7181D in power-down mode. 30 ELPF Output External Loop Filter Output. The recommended external loop filter must be connected to this pin (see the Recommended External Loop Filter Components section). 31 PVDD Power PLL Supply Voltage (1.8 V). 32 FB Input Fast Blank Input. Fast switch between CVBS and RGB analog signals. |
类似零件编号 - ADV7181D |
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类似说明 - ADV7181D |
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