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ADP1053ACPZ-R7 数据表(PDF) 8 Page - Analog Devices |
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ADP1053ACPZ-R7 数据表(HTML) 8 Page - Analog Devices |
8 / 84 page ADP1053 Data Sheet Rev. A | Page 8 of 84 Parameter Test Conditions/Comments Min Typ Max Unit SERIAL BUS TIMING See Figure 3 Clock Frequency 100 400 kHz Glitch Immunity, tSW 50 ns Bus Free Time, tBUF 1.3 μs Start Setup Time, tSU;STA 0.6 μs Stop Setup Time, tSU;STO 0.6 μs Start Hold Time, tHD;STA 0.6 μs SCL Low Time, tLOW 0.6 μs SCL High Time, tHIGH 0.6 μs SCL, SDA Rise Time, tR 20 ns SCL, SDA Fall Time, tF 20 ns Data Setup Time, tSU;DAT 100 ns Data Hold Time, tHD;DAT Read 125 ns Write 300 ns EEPROM EEPROM Update Time Time from update command to EEPROM update completed (TJ = 25°C) 40 ms Reliability Endurance1 TJ = 85°C 10,000 Cycles TJ = 125°C 1000 Cycles Data Retention2 TJ = 85°C 20 Years TJ = 125°C 10 Years 1 Endurance is qualified as per JEDEC Standard 22, Method A117, and is measured at −40°C, +25°C, +85°C, and +125°C. Endurance conditions are subject to change pending EEPROM qualification. 2 Retention lifetime equivalent at junction temperature (TJ) = 125°C as per JEDEC Standard 22, Method A117. The derated lifetime is subject to change pending EEPROM qualification. SCL SDA PS tBUF tHD;STA tHD;DAT tHIGH tSU;DAT tHD;STA tSU;STA tSU;STO tLOW tR tF SP Figure 3. Serial Bus Timing Diagram |
类似零件编号 - ADP1053ACPZ-R7 |
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类似说明 - ADP1053ACPZ-R7 |
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