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ADF4196 数据表(PDF) 6 Page - Analog Devices |
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ADF4196 数据表(HTML) 6 Page - Analog Devices |
6 / 28 page ADF4196 Data Sheet Rev. B | Page 6 of 28 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 CMR 2 AOUT 3 SW3 4 AGND1 5 RFIN– 6 RFIN+ 7 AVDD 24 VP2 23 RSET 22 AGND2 21 DGND3 20 VP1 19 LE 18 DATA 17 CLK 8 DVDD1 ADF4196 TOP VIEW (Not to Scale) PIN 1 INDICATOR NOTES 1. THE EXPOSED PADDLE MUST BE CONNECTED TO THE GROUND PLANE. Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 CMR Common-Mode Reference Voltage for the Output Voltage Swing of the Differential Amplifier. Internally biased to three-fifths of VP3. Requires a 0.1 µF capacitor to the ground plane. 2 AOUT Differential Amplifier Output. This pin is the differential amplifier output to tune the external VCO. 3 SW3 Fast Lock Switch 3. This switch is closed when the SW3 timeout counter is active. 4 AGND1 Analog Ground. This is the ground return pin for the differential amplifier and the RF section. 5 RFIN− Complementary Input to the RF Prescaler. This pin must be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. 6 RFIN+ Input to the RF Prescaler. This small-signal input is ac-coupled to the external VCO. 7 AVDD Power Supply Pin for the RF Section. Nominally 3 V. Place a 100 pF decoupling capacitor to the ground plane as close as possible to this pin. 8 DVDD1 Power Supply Pin for the N Divider. DVDD1 should be at the same voltage as AVDD. Place a 0.1 µF decoupling capacitor to the ground plane as close as possible to this pin. 9 DGND1 Ground Return Pin for DVDD1. 10 DVDD2 Power Supply Pin for the REFIN Buffer and R Divider. Nominally 3 V. Place a 0.1 µF decoupling capacitor to the ground plane as close as possible to this pin. 11 REFIN Reference Input. This CMOS input has a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. 12 DGND2 Ground Return Pin for DVDD2 and DVDD3. 13 DVDD3 Power Supply Pin for the Serial Interface Logic. Nominally 3 V. 14 SDGND Ground Return Pin for the Digital Σ-Δ Modulator. 15 SDVDD Power Supply Pin for the Digital Σ-Δ Modulator. Nominally 3 V. Place a 0.1 µF decoupling capacitor to the ground plane as close as possible to this pin. 16 MUXOUT Multiplexer Output. This multiplexer output allows the lock detect, the scaled RF, or the scaled reference frequency to be accessed externally (see Figure 35 for details). 17 CLK Serial Clock Input. Data is clocked into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. 18 DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high impedance CMOS input. 19 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that is selected by the three LSBs. 20 VP1 Power Supply Pin for the Phase Frequency Detector (PFD). Nominally 5 V, VP1 should be at the same voltage as VP2. Place a 0.1 µF decoupling capacitor to the ground plane as close as possible to this pin. 21 DGND3 Ground Return Pin for VP1. 22 AGND2 Ground Return Pin for VP2. |
类似零件编号 - ADF4196 |
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类似说明 - ADF4196 |
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