数据搜索系统,热门电子元器件搜索 |
|
M1008G-P28-T 数据表(PDF) 5 Page - Unisonic Technologies |
|
M1008G-P28-T 数据表(HTML) 5 Page - Unisonic Technologies |
5 / 11 page M1008 Preliminary CMOS IC UNISONICTECHNOLOGIESCO.,LTD 5 of 11 www.unisonic.com.tw QW-R502-434.a TIMING SPECIFICATION PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT 3-Channel Pixel Rate tPRA 100 ns 2-Channel Pixel Rate tPRB 66 ns 1-Channel Pixel Rate tPRC 40 ns ADCCLK Pulse Width tADCLK 16 ns CDSCLK1 Pulse Width tC1 12 ns CDSCLK2 Pulse Width tC2 12 ns CDSCLK1 Falling to CDSCLK2 Rising tC1C2 0 ns ADCCLK Rising to CDSCLK1 Falling tADC1 0 ns ADCCLK Rising to CDSCLK2 Falling tADC2 0 ns Analog Sampling Delay tAD 5 ns 3-CHANNEL Mode Only CDSCLK2 Falling to CDSCLK1 Rising taC2C1 30 ns CDSCLK2 Falling to ADCCLK Rising taC2ADR 30 ns 2-CHANNEL Mode Only CDSCLK2 Falling to ADCCLK Rising tbC2ADR 30 ns CDSCLK1 Rising to ADCCLK Rising tbC1ADR 15 ns CDSCLK2 Falling to CDSCLK1 Rising tbC2C1 15 ns 1-CHANNEL Mode Only CDSCLK2 Falling to ADCCLK Rising tcC2ADR 20 ns CDSCLK1 Rising to ADCCLK Falling tcC1ADF 0 ns CDSCLK2 Falling to CDSCLK1 Rising tcC2C1 15 ns SERIAL INTERFACE Maximum SCLK Frequency fSCLK 10 MHz SLOAD to SCLK Setup Time tLS 10 ns SCLK to SLOAD Hold Time tLH 10 ns SDATA to SCLK Rising Setup Time tDS 10 ns SCLK Rising to SDARA Hold Time tDH 10 ns Falling to SDATA Valid tRDV 10 ns DATA OUTPUT Output Delay tOD 8 ns Latency(Pipeline Delay) 9 Cycles |
类似零件编号 - M1008G-P28-T |
|
类似说明 - M1008G-P28-T |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |