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LS3718-S28-R 数据表(PDF) 6 Page - Unisonic Technologies

部件名 LS3718-S28-R
功能描述  20-BIT SERIAL TO PARALLEL CONVERTER
Download  8 Pages
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制造商  UTC [Unisonic Technologies]
网页  http://www.utc-ic.com
标志 UTC - Unisonic Technologies

LS3718-S28-R 数据表(HTML) 6 Page - Unisonic Technologies

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LS3718
CMOS IC
UNISONICTECHNOLOGIESCO.,LTD
6 of 8
www.unisonic.com.tw
QW-R121-015.A
FUNCTION DESCRIPTION
RESET
When the CLR terminal is "L" level, all latches are reset and all of parallel output are "L" level.
Normally, the CLR terminal should be "H" level.
DATA TRANSMISSION
When the STB terminal is "H" level and input the clock signal to the CLK terminal, the serial data input the DATA
terminal and shift in the shift register by synchronizing at rising edge of the clock signal.
When the STB terminal is changed to "L" level, the data in the shift register are transferred to the latch.
Even if the STB terminal is "L" level, the input clock signal shift the data in the shift register, therefore, the clock
signal controlled is needed.
CASCADE CONNECTION
The serial data input from DATA terminal and output from the SO terminal through internal shift register
unrelated to the CLR and STB status.
Furthermore, the 4 input terminals have a hysteresis characteristic by using the schmitt trigger structure to
decrease the noise.
CLK
STB
CLR
DESCRIPTION
X
X
L
All latch are reset (the data in the shift register is not change). All of
parallel outputs are "L".
H
H
The serial data input from DATA terminal to the shift register (the data in
the latch is not change).
L
H
The data in the shift register transfer to the latch. And the data in the
latch output from the parallel output.
L
H
The CLK input in the STB="L" and CLR="H" state, the data shift in the
shift register and latched data also change in accordance with the shift
register.
Note: X: Don’t care


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