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ISL267450AIUZ 数据表(PDF) 7 Page - Intersil Corporation |
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ISL267450AIUZ 数据表(HTML) 7 Page - Intersil Corporation |
7 / 17 page ISL267440, ISL267450A 7 FN7708.0 December 5, 2011 Timing Specifications Limits established by characterization and are not production tested. VDD = 3.0V to 3.6V, fSCLK =18MHz, fS =1MSPS, VREF = 2.0V; VDD = 4.75V to 5.25V, fSCLK =18MHz, fS = 1MSPS, VREF =2.5V; VCM = VREF unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +85°C. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7) UNITS fSCLK Clock Frequency 0.01 18 MHz tSCLK Clock Period 55 ns tACQ Acquisition Time 200 ns tCONV Conversion Time 888 ns tCSW CS Pulse Width 10 ns tCSS CS Falling Edge to SCLK Falling Edge Setup Time 10 ns tCDV CS Falling Edge to SDATA Valid 20 ns tCLKDV SCLK Falling Edge to SDATA Valid 40 ns tSDH SCLK Falling Edge to SDATA Hold 10 ns tSW SCLK Pulse Width 0.4 x tSCLK ns tDISABLE SCLK Falling Edge to SDATA Disable Time (Note 9) Extrapolated back to true bus relinquish 10 35 ns tQUIET Quiet Time Before Sample 60 ns NOTE: 9. During characterization, tDISABLE is measured from the release point with a 10pF load (see Figure 4) and the equivalent timing using the AD7440/450A loading (25pF) is calculated. FIGURE 3. SERIAL INTERFACE TIMING DIAGRAM C YC LE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CSB SC LK DO UT 18M H z = 55.5556ns PER IO D 1 D0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 D0 D0 MSB BIT10 BIT 9 BIT 8 BIT7 BIT 6 BIT 5 BIT4 BIT3 BIT2 BIT1 T/H TO HO LD M O DE , DOUT VA LID T/H TO SA M PLE M O D E DOUT TR ISTA TE DO UT D0 D0 D0 D0 MSB BIT 8 BIT7 BIT 6 BIT 5 BIT4 BIT3 BIT2 BIT1 ISL267440 DATA O U TPUT ISL267450A DATA O U TPUT BIT 0 BIT0 FIGURE 4. EQUIVALENT LOAD CIRCUIT OUTPUT PIN CL 10pF VDD 2.85k Ω RL |
类似零件编号 - ISL267450AIUZ |
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类似说明 - ISL267450AIUZ |
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