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SI6924AEDQ 数据表(PDF) 2 Page - Vishay Siliconix |
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SI6924AEDQ 数据表(HTML) 2 Page - Vishay Siliconix |
2 / 12 page www.vishay.com 2 Document Number: 72215 S-81056-Rev. B, 12-May-08 Vishay Siliconix Si6924AEDQ FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION Notes: a. Surface Mounted on FR4 board. Figure 3. Ordering Information: Si6924AEDQ-T1-GE3 (Lead (Pb)-free and Halogen-free) Si6924AEDQ D S1 S1 G1 1 2 3 4 8 7 6 5 D S2 S2 G2 TSSOP-8 Top View Figure 4. G1 S1 G2 S2 N-Channel N-Channel 3.3 k Ω 3.3 k Ω *D *D *Thermal connection to drain pins is required to achieve specific performance. ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Symbol 10 s Steady State Unit Drain-Source Voltage, Source-Drain Voltage VDS 28 V Gate-Source Voltage VGS ± 14 Continuous Drain-to-Source Current (TJ = 150 °C) a TA = 25 °C ID 4.6 4.1 A TA = 70 °C 3.7 3.2 Pulsed Drain-to-Source Current IDM 20 Pulsed Source Current (Diode Conduction)a IS 1.2 0.9 Maximum Power Dissipationa TA = 25 °C PD 1.3 1.0 W TA = 70 °C 0.84 0.64 Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Unit Maximum Junction-to-Ambienta t ≤ 10 s RthJA 71 95 °C/W Steady State 96 125 Maximum Junction-to-Foot (Drain) Steady State RthJF 56 70 |
类似零件编号 - SI6924AEDQ_08 |
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类似说明 - SI6924AEDQ_08 |
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