LC863548C/40C/32C/28C/24C/20C/16C

No.A0118-3/17

Serial interfaces

• IIC-bus compliant serial interface (Multi-master type)

Consists of a single built-in circuit with two I/O channels. The two data lines and two clock lines can be connected

internally.

PWM output

• 3-channels × 7-bit PWM

Timer

• Timer 0 : 16-bit timer/counter

With 2-bit prescaler + 8-bit programmable prescaler

Mode 0 : Two 8-bit timers with a programmable prescaler

Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter

Mode 2 : 16-bit timer with a programmable prescaler

Mode 3 : 16-bit counter

The resolution of timer is 1 tCYC.

• Timer 1 : 16-bit timer/ PWM

Mode 0 : Two 8-bit timers

Mode 1 : 8-bit timer + 8-bit PWM

Mode 2 : 16-bit timer

Mode 3 : A variable-bit PWM (9 to 16 bits)

In mode 0/1, the resolution of timer/PWM is 1 tCYC

In mode 2/3, the resolution of timer/PWM is selectable by program ; tCYC or 1/2 tCYC

• Base timer

Generate every 500ms overflow for a clock application

(using 32.768kHz crystal oscillation for the base timer clock)

Generate every 976

µs, 3.9ms, 15.6ms, 62.5ms overflow

(using 32.768kHz crystal oscillation for the base timer clock)

Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler

output of Timer 0

Remote control receiver circuit (connected to the P73/INT3/T0IN terminal)

• Noise rejection function

• Polarity switching

Watchdog timer

External RC circuit is required

Interrupt or system reset is activated when the timer overflows

ROM correction function

Max 128-bytes/2 addresses

Interrupts

• 13 sources 8 vectored interrupts

1. External Interrupt INT0

2. External Interrupt INT1

3. External Interrupt INT2, Timer/counter T0L (Lower 8-bits)

4. External Interrupt INT3, base timer

5. Timer/counter T0H (Upper 8-bits)

6. Timer T1H, Timer T1L

7. Vertical synchronous signal interrupt (VS), horizontal line (HS)

8. IIC, Software

• Interrupt priority control

Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible.

Low or high priority can be assigned to the interrupts from 3 to 8 listed above.

For the external interrupt INT0 and INT1, low or highest priority can be set.