LC863G64A/56A/48A/40A/32A/28A/24A

No.A0548-4/21

Interrupts

• 18 source 10 vectored interrupts

1. External Interrupt INT0

2. External Interrupt INT1

3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits)

4. External Interrupt INT3, base timer

5. Timer/counter T0H (Upper 8 bits)

6. Timer T1H, T1L

7. SIO0, UART receive

8. Data slicer, UART transmit

9. Vertical synchronous signal interrupt (VS), horizontal line (HS), AD

10. IIC, Port 0

• Interrupt priority control

Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible.

Low or high priority can be assigned to the interrupts from 3 to 10 listed above.

For the external interrupt INT0 and INT1, low or highest priority can be set.

Sub-routine Stack Level

• A maximum of 128 levels (stack is built in the internal RAM)

Multiplication/Division Instruction

• 16 bits × 8 bits (7 instruction cycle times)

• 16 bits ÷ 8 bits (7 instruction cycle times)

3 Oscillation Circuits

• Built-in RC oscillation circuit used for the system clock

• Built-in VCO circuit used for the system clock and OSD

• X’tal oscillation circuit used for base timer, system clock and PLL reference

Standby Function

• HALT mode

The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped.

This mode can be released by the interrupt request or the system reset.

• HOLD mode

The HOLD mode is used to stop the oscillations; RC (internal), VCO and X’tal oscillations. This mode can be

released by the following conditions.

- Pull the reset terminal (RES) to low level.

- Feed the selected level to either P70/INT0 or P71/INT1.

- Input the interrupt condition to Port 0.

Package

• DIP42S(600mil): Lead-free type

• QIP48E(14×14) : Lead-free type

Development Tools

• Flash EEPROM: LC86F3G64A

• Emulator:

Special ROM monitor tool

(When debugging it, one terminal in the I/O port is used as a pin only for the tool)