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FM31T376 数据表(PDF) 6 Page - Ramtron International Corporation |
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FM31T376 数据表(HTML) 6 Page - Ramtron International Corporation |
6 / 26 page FM31T372/374/376/378-G Rev. 1.1 Apr. 2011 Page 6 of 26 Figure 5. Comparator as Early Power-Fail Warning The voltage on the PFI input pin is compared to an onboard 1.2V reference. When the PFI input voltage drops below this threshold, the comparator will drive the CAL/PFO pin to a low state. The comparator has 100 mV (max) of hysteresis to reduce noise sensitivity, only for a rising PFI signal. For a falling PFI edge, there is no hysteresis. The comparator is a general purpose device and its application is not limited to the NMI function. The comparator is not integrated into the special function registers except as it shares its output pin with the CAL output. When the CAL mode is invoked by setting the CAL bit (register 00h, bit 2), the CAL/PFO output pin is driven with a 512 Hz square wave and the comparator will be ignored. Since most users only invoke the CAL mode during production, this should have no impact on system operations using the comparator. Event Counter The FM31T37x offers the user two battery-backed event counters. Input pins CNT1 and CNT2 are programmable edge detectors. Each clocks a 16-bit counter. When an edge occurs, the counters will increment their respective registers. Counter 1 is located in registers 0Dh and 0Eh, Counter 2 is located in registers 0Fh and 10h. These register values can be read anytime VDD is above VTP, and they will be incremented as long as a valid VBAK power source is provided. To read, set the RC bit register 0Ch bit 3 to 1. This takes a snapshot of all four counter bytes allowing a stable value even if a count occurs during the read. The registers can be written by software allowing the counters to be cleared or initialized by the system. Counts are blocked during a write operation. The two counters can be cascaded to create a single 32-bit counter by setting the CC control bit (register 0Ch). When cascaded, the CNT1 input will cause the counter to increment. CNT2 is not used in this mode. Figure 6. Event Counter The control bits for event counting are located in register 0Ch. Counter 1 Polarity is bit C1P, bit 0; Counter 2 Polarity is C2P, bit 1; the Cascade Control is CC, bit 2; and the Read Counter bit is RC bit 3. The polarity bits must be set prior to setting the counter value(s). If a polarity bit is changed, the counter may inadvertently increment. If the counter pins are not being used, tie them to ground. Event Counter Driven Interrupt Output The event counter driven interrupt is a battery backed open-drain output (/INT). A 100ms active low pulse generated for the host microcontroller upon changes on either CNT1 or CNT2 pins. The CNT2 pin will not generate an interrupt if the CC bit is set to „1‟ (counter set to cascaded 32-bit mode). Figure 7. Event Counter Driven Interrupt Output Serial Number A memory location to write a 64-bit serial number is provided. It is a writeable nonvolatile memory block that can be locked by the user once the serial number is set. The 8 bytes of data and the lock bit are all accessed via the device ID for the processor companion. Therefore the serial number area is separate and distinct from the memory array. The serial number registers can be written an unlimited number of times, so these locations are general purpose memory. However once the lock bit is set the values cannot be altered and the lock cannot be removed. Once locked the serial number registers can still be read by the system. FM31T37x INT MCU INT Event occur 100 ms 16-bit Counter CNT1 CC CNT2 C1P C2P 16-bit Counter + - 1.2V ref Regulator VDD FM31T37x To MCU NMI input CAL/PFO PFI |
类似零件编号 - FM31T376 |
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类似说明 - FM31T376 |
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