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GS7032-CVME3 数据表(PDF) 4 Page - Gennum Corporation |
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GS7032-CVME3 数据表(HTML) 4 Page - Gennum Corporation |
4 / 9 page 14583 - 04 4 of 9 PIN CONNECTIONS GS7032 TOP VIEW 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC BYPASS NC VEE NC NC VEE SDO SDO VEE PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PCLKIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 RESET PIN DESCRIPTIONS NUMBER SYMBOL TYPE DESCRIPTION 1-10 PD9 - PD0 I CMOS or TTL compatible parallel data inputs. PD0 is the LSB and PD9 is the MSB. 11 PCLKIN I CMOS or TTL compatible parallel clock input. 12 VEE3 - Most negative power supply connection for parallel data and clock inputs. 13 VCC3 - Most positive power supply connection for parallel data and clock inputs. 14 RSV2 I Reserved pin. Do not connect. 15, 19, 21, 27, 28, 30, 32, 37 NC I No connect. 16 RSV1 I Reserved pin. Always connect to VCC. 17 VCC2 - Most positive power supply connection for internal logic and digital circuits. 18 VEE2 - Most negative power supply connection for internal logic and digital circuits. 20 LOCK O TTL level which is high when the internal PLL is locked. 22 RSET I External resistor used to set the data output amplitude for SDO and SDO. 23, 26, 29 VEE - Most negative power supply connection for shielding (not connected). 24, 25 SDO, SDO O Primary, current mode, 75 Ω cable driving output (inverse and true) 31 BYPASS I When high, the SMPTE Scrambler and NRZ encoder are bypassed. |
类似零件编号 - GS7032-CVME3 |
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类似说明 - GS7032-CVME3 |
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