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SM5M2 数据表(PDF) 10 Page - Sharp Corporation |
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SM5M2 数据表(HTML) 10 Page - Sharp Corporation |
10 / 28 page SM5M2 - 10 - Program Counter PC and Stack Register SR A ROM address is specified by the program counter (PC). The PC comprises 12-bit where 6- bit (PU) are used to specify the page (see Fig. 6) and 6-bit (PL) are used to specify the step. PU is a register and PL is a binary counter. The table reference instruction PAT executes a similar operation to that of the subroutine jump and uses one level of the stack register. Program Memory (ROM) The ROM is used for program storage. The ROM capacity of the SM5M2 is 3 072-step . The ROM is organized into 48-page where one page is organized into 64-step. Program counter PC PU PL Push Pop SR ( level 1 ) SR ( level 2 ) SR ( level 3 ) SR ( level 4 ) MSB LSB Stack register SR Page Step Fig. 6 Program Counter PC and Stack Register SR Page 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH PU 000000 Program start First page of subroutine TRS Interrupt Standby release Table reference page PAT 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 Page 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH PU 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 Page 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH PU 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 Last page Fig. 7 ROM Organization |
类似零件编号 - SM5M2 |
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类似说明 - SM5M2 |
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