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STP1612PW05MTR 数据表(PDF) 11 Page - STMicroelectronics |
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STP1612PW05MTR 数据表(HTML) 11 Page - STMicroelectronics |
11 / 35 page STP1612PW05 Electrical characteristics Doc ID 15819 Rev 4 11/35 Figure 3. Test circuit for electrical characteristics Table 10. Switching characteristics (VDD = 5.0 V) TA = -40 ~ 125 °C Symbol Characteristics Conditions Min. Typ. Max. Unit tSU0 Setup time SDI - CLK ↑ VDD = 5.0 V VIH = VDD VIL = GND Rext = 460 Ω VLED = 4.5 V RL = 152 Ω CL = 10 pF C1 = 100 nF C2 = 10 μF IO = 20 mA 1 ns tSU1 LE ↑ – DCLK ↑ 1 ns tSU2 LE ↓ – DCLK ↑ 5 ns tH0 Hold time CLK ↑ - SDI 3 ns tH1 CLK ↑ - LE ↓ 7 ns tPD0 Propagation delay time CLK - SDO 30 40 ns tPD1 PWCLK-OUTn4 (1) 1. Refer to the timing waveform, where n = 0, 1, 2, 3. 100 ns tPD2 LE – SDO(2) 2. In timing of “read configuration” and “read error status code”, the next CLK rising edge should be tPD2 after the falling edge of LE. 30 40 ns tDL1 Stagger delay time OUTn4 + 1 (1) 40 ns tDL2 OUTn4 + 2 (1) 80 ns tDL3 OUTn4 +3 (1) 120 ns tw(L) Pulse width LE 5 ns tw( CLK) CLK 20 ns tw(PWCLK) PWCLK 20 ns tON Output rise time of output ports 10 ns tOFF Output fall time of output ports 6 ns tEDD Error detection minimum duration (3) 3. Refer to Figure 5 on page 13. 1µs PWCLK CLK LE DD V EXT - R GND SDO OUT0 . .. Generator Function DD I V IH=VDD V IL=G ND waveform input Logic SDI O UT15 OUT I V IH,VIL V DD R ext IOL I OH |
类似零件编号 - STP1612PW05MTR |
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类似说明 - STP1612PW05MTR |
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