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TS3DDR3812RUAR 数据表(PDF) 7 Page - Texas Instruments |
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TS3DDR3812RUAR 数据表(HTML) 7 Page - Texas Instruments |
7 / 18 page CL (see Note A) TEST CIRCUIT S1 2 × VDD Open GND RL RL NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics:PRR ≤10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. 50 Ω VG1 VDD DUT 50 Ω VIN 50 Ω VG2 50 Ω VI TEST RL S1 V∆ CL VDD Vin tPLZ/tPZL 2 × VDD 200 Ω GND 4 pF 0.3 V Input Generator Input Generator VO tPHZ/tPZH GND 200 Ω VDD 4 pF 0.3 V tPZL VOH - 0.3 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VCC/2 VDC/2 Output Control (VIN) VOH VOL + 0.3 V VOH VOL 0 V tPZH tPLZ tPHZ Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) VOL VO VSEL VO 3.3 V ± 0.3 V 3.3 V ± 0.3 V 1.65 V 1.65 V 3.33 V TS3DDR3812 www.ti.com SCDS314A – FEBRUARY 2011 – REVISED MARCH 2011 PARAMETER MEASUREMENT INFORMATION Enable and Disable Times Figure 5. Test Circuit and Voltage Waveforms Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s) :TS3DDR3812 |
类似零件编号 - TS3DDR3812RUAR |
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类似说明 - TS3DDR3812RUAR |
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