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BD3403FV 数据表(PDF) 5 Page - Rohm |
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BD3403FV 数据表(HTML) 5 Page - Rohm |
5 / 16 page Technical Note 5/15 www.rohm.com 2010.10 - Rev.A © 2010 ROHM Co., Ltd. All rights reserved. BD3403FV,BD3861FS,BD3883FS ● Control signal specifications 1. Signal Timing Conditions ・ Data is read on the rising edge of the clock. ・ Latch is read on the falling edge of the clock. ・ Latch signal must terminate with the LOW state. ・ To avoid malfunctions, clock and data signals must terminate with the LOW state. 1byte=8bit Fig.1 Parameter Symbol Limits Unit Min. Typ. Max. Minimum Clock Width twc 2.0 - - µs Minimum Data Width twd 2.0 - - µs Minimum Latch Width tw1 2.0 - - µs Data Set-up Time (DATA CLK) Tsd 1.0 - - µs Data Hold Time (CLK DATA) Thd 1.0 - - µs Latch Set-up Time (CLK LATCH) ts1 1.0 - - µs Latch Hold Time (DATA LATCH) th1 1.0 - - µs Latch Low Set-up Time ts 1.0 - - µs Latch Low Hold Time th 1.0 - - µs 2. Voltage Conditions for Control Signals (BD3403FV, BD3861FS) Parameter Condition Limits Unit Min. Typ. Max. “H” Input Voltage Vcc=6.5 to 9.5V 2.6 - 5.5 V “L” Input Voltage Vcc=6.5 to 9.5V 0 - 1.1 V 3. Voltage Conditions for Control Signals (BD3883FS) Parameter Condition Limits Unit Min. Typ. Max. “H” Input Voltage Vcc=6.5 to 9.5V 2.2 - 5.5 V “L” Input Voltage Vcc=6.5 to 9.5V 0 - 1.0 V SC (CLOCK) SI DATA LATCH thd thd th ts ts1 th1 tsd twc twd twd tw1 tsu DATA DATA LATCH 90% 90% 90% 90% 10% 10% 10% 90% 90% 90% 90% 90% 10% 10% 10% twc Low |
类似零件编号 - BD3403FV |
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类似说明 - BD3403FV |
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