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TMP103CYFFR 数据表(PDF) 10 Page - Texas Instruments

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部件名 TMP103CYFFR
功能描述  Low-Power, Digital Temperature Sensor with Two-Wire Interface in WCSP
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TMP103CYFFR 数据表(HTML) 10 Page - Texas Instruments

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TMP103
SBOS545A
– FEBRUARY 2011 – REVISED MARCH 2011
www.ti.com
SERIAL BUS ADDRESS
SLAVE MODE OPERATIONS
To communicate with the TMP103, the master must
The TMP103 can operate as a slave receiver or slave
first address slave devices via a slave address byte.
transmitter. As a slave device, the TMP103 never
The slave address byte consists of seven address
drives the SCL line.
bits, and a direction bit that indicates the intent of
executing a read or write operation.
Slave Receiver Mode
The TMP103 is available in eight versions, each with
The first byte transmitted by the master is the slave
a different slave address, as shown in Table 9. These
address, with the R/W bit low. The TMP103 then
addresses can be used as either a location or a
acknowledges reception of a valid address. The next
temperature zone designator.
byte transmitted by the master is the Pointer
Register. The TMP103 then acknowledges reception
Table 9. Device Slave Addresses
of the Pointer Register byte. The next byte is written
to the register addressed by the Pointer Register. The
TWO-WIRE
TEMPERATURE
PRODUCT
TMP103 acknowledges reception of the data byte.
ADDRESS
ZONE
The master can terminate data transfer by generating
TMP103A
1110000
Zone1
a START or STOP condition.
TMP103B
1110001
Zone2
TMP103C
1110010
Zone3
Slave Transmitter Mode
TMP103D
1110011
Zone4
The first byte transmitted by the master is the slave
TMP103E
1110100
Zone5
address,
with
the
R/W
bit
high.
The
slave
TMP103F
1110101
Zone6
acknowledges reception of a valid slave address. The
next byte is transmitted by the slave of the register
TMP103G
1110110
Zone7
indicated
by
the
Pointer
Register.
The
master
TMP103H
1110111
Zone8
acknowledges reception of the data byte. The master
can
terminate
data
transfer
by
generating
a
WRITING/READING OPERATION
Not-Acknowledge on reception of the data byte, or
generating a START or STOP condition.
Accessing a particular register on the TMP103 is
accomplished by writing the appropriate value to the
GENERAL CALL
Pointer Register. The value for the Pointer Register is
the first byte transferred after the slave address byte
The TMP103 responds to a two-wire General Call
with the R/W bit low. Every write operation to the
address (0000000) if the eighth bit is '0'. The device
TMP103 requires a value for the Pointer Register
acknowledges
the
General
Call
address
and
(see Figure 12).
responds to commands in the second byte. If the
second byte is 00000110, the TMP103 internal
When reading from the TMP103, the last value stored
registers are reset to power-up values. The TMP103
in the Pointer Register by a write operation is used to
does not support the General Address acquire
determine which register is read by a read operation.
command.
To change the register pointer for a read operation, a
new value must be written to the Pointer Register.
HIGH-SPEED (Hs) MODE
This action is accomplished by issuing a slave
address byte with the R/W bit low, followed by the
In order for the two-wire bus to operate at frequencies
Pointer
Register
byte.
No
additional
data
are
above 400kHz, the master device must issue an
required. The master can then generate a START
Hs-mode master code (00001xxx) as the first byte
condition and send the slave address byte with the
after a START condition to switch the bus to
R/W bit high to initiate the read command. See
high-speed
operation.
The
TMP103
does
not
Figure 13 for details of this sequence. If repeated
acknowledge this byte, but switches its input filters on
reads from the same register are desired, it is not
SDA and SCL and its output filters on SDA to operate
necessary to continually send the Pointer Register
in Hs-mode, allowing transfers at up to 3.4MHz. After
bytes; the TMP103 remembers the Pointer Register
the Hs-mode master code has been issued, the
value until it is changed by the next write operation,
master transmits a START condition followed by a
or the TMP103 is reset.
two-wire slave address to initiate a data transfer
operation. The bus continues to operate in Hs-mode
until a STOP condition occurs on the bus. Upon
receiving the STOP condition, the TMP103 switches
the input and output filters back to the default
fast-mode operation.
10
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© 2011, Texas Instruments Incorporated
Product Folder Link(s): TMP103


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