数据搜索系统,热门电子元器件搜索 |
|
AD7280A 数据表(PDF) 6 Page - Analog Devices |
|
AD7280A 数据表(HTML) 6 Page - Analog Devices |
6 / 48 page AD7280A Rev. 0 | Page 6 of 48 TIMING SPECIFICATIONS VDD = 8 V to 30 V, VSS = 0 V, DVCC = AVCC = VREG, VDRIVE = 2.7 V to 5.5 V, TA = −40°C to +105°C, unless otherwise noted. Table 3. Parameter1 Min Typ Max Unit Description tCONV ADC conversion time 425 560 695 ns −40°C to +85°C 425 720 ns −40°C to +105°C tACQ ADC acquisition time, Bits[D6:D5] of the control register set to 00 340 400 465 ns −40°C to +85°C 340 470 ns −40°C to +105°C tACQ ADC acquisition time, Bits[D6:D5] of the control register set to 01 665 800 1010 ns −40°C to +85°C 665 1030 ns −40°C to +105°C tACQ ADC acquisition time, Bits[D6:D5] of the control register set to 10 1005 1200 1460 ns −40°C to +85°C 1005 1510 ns −40°C to +105°C tACQ ADC acquisition time, Bits[D6:D5] of the control register set to 11 1340 1600 1890 ns −40°C to +85°C 1340 1945 ns −40°C to +105°C tDELAY 200 250 ns Propagation delay between the falling edges of CNVST of adjacent parts in the daisy chain tWAIT 5 μs Time required between the end of conversions and the beginning of readback of the conversion results fSCLK 1 MHz Frequency of serial read clock tQUIET 200 ns Minimum quiet time required between the end of a serial read and the start of the next conversion t12 0.4 50 μs CNVST low pulse t2 10 ns CS falling edge to SCLK rising edge t3 20 ns Delay from CS falling edge until SDO is three-state disabled t4 5 ns SDI setup time prior to SCLK falling edge t5 4 ns SDI hold time after SCLK falling edge t63 28 ns Data access time after SCLK rising edge t7 20 ns SCLK to data valid hold time t8 0.45 × tSCLK ns SCLK high pulse width t9 0.45 × tSCLK ns SCLK low pulse width t104 100 ns CS rising edge to SCLK rising edge t11 10 ns CS rising edge to SDO high impedance t12 3 μs CS high time required between each 32-bit write/read command 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. All timing specifications given are with a 25 pF load capacitance. 2 Maximum allowed CNVST low pulse time to ensure that a software power-down state is not entered when the CNVST pin is not gated. 3 Time required for the output to cross 0.4 V or 2.4 V. 4 t10 applies when using a continuous SCLK. Guaranteed by design. Timing Diagram t8 t10 THREE-STATE THREE-STATE SCLK SDO SDI LSB MSB MSB – 1 MSB MSB – 1 32 4 3 2 1 LSB t12 t2 3 t 6 t t7 t4 t5 t11 t9 CS Figure 2. Serial Interface Timing Diagram |
类似零件编号 - AD7280A |
|
类似说明 - AD7280A |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |