AN-8027

© 2009 Fairchild Semiconductor Corporation

www.fairchildsemi.com

Rev. 1.0.0 • 8/26/09

3

ISENSE

IAC

VRMS

VEA

IEA

R

M

R

M

R

RMS1

R

RMS2

R

RMS3

C

RMS1

C

RMS2

R

IAC

I

AC

V

IN

I

L

R

CS1

R

F1

C

F1

I

MO

R

IC

C

IC1

C

IC2

+

-

Drive logic

OPFC

2.5V

R

VC

R

VC1

R

VC2

FBPFC

R

FB1

R

FB2

V

O

VREF

Figure 5. Gain Modulation Block

I

AC

I

L

1

M

MO

CS

R

I

R

Figure 6. Inductor Current Shaping

The voltage control loop regulates PFC output voltage

using internal error amplifier such that the FBPFC voltage

is same as internal reference of 2.5V.

Brownout Protection

FAN480X has a built-in internal brownout protection

comparator monitoring the voltage of the VRMS pin. Once

the VRMS pin voltage is lower than 1.05V (0.9V for

FAN4802L), the PFC stage is shutdown to protect the

system from over current. The FAN480X starts up the

(1.65V for FAN4802L).

Two-Level PFC Output

To improve system efficiency at low AC line voltage and

light load condition, FAN480X provides two-level PFC

output voltage. As shown in Figure 7, FAN480X monitors

internal current source of 20

This causes the PFC output voltage to reduce when 20

is enabled, calculated as:

12

22

2

(2 5 20

)

+

=×

×

FB

FB

OPFC

FB

FB

RR

V. -

μAR

R

(5)

It is typical to set the second boost output voltage as

Figure 7. Block of Two-Level PFC Output

Oscillator

The internal oscillator frequency of FAN480X is

determined by the timing resistor and capacitor on RT/CT

pin. The frequency of the internal oscillator is given by:

1

0.56

360

OSC

TT

T

f

R CC

=

⋅⋅

+

(6)

Because the PWM stage of FAN480X generally uses a

forward converter, it is required to limit the maximum duty

cycle at 50%. To have a small tolerance of the maximum

duty cycle, a frequency divider with toggle flip-flops is

used, as illustrated in Figure 8. The operation frequency of

PFC and PWM stage is one quarter (1/4) of the oscillator

frequency. (For FAN4800C and FAN4802/2L, the

operation frequencies for PFC and PWM stages are one

quarter (1/4) and one half (1/2) of the oscillator frequency,

respectively).

The dead time for the PFC gate drive signal is determined

by the equation:

360

DEAD

T

tC

=

(7)

The dead time should be smaller than 2% of switching

period to minimize line current distortion around line zero

crossing.

RT/

CT

VREF

OSC

TQ

T-FF

T

Q

OPWM (FAN4800C, FAN4802/2L)

OPFC, OPWM

T-FF

Figure 8. Oscillator Configuration